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SYNOPSYS INC (SNPS) Patents: Active, 2022

SYNOPSYS INC Active Patents

178 granted patents the USPTO still lists as patented, newest filing first, as the USPTO Open Data Portal records them; the company is the first-named applicant. The application number opens the full record at Patent Center.

  • 2022-12-29: Application 18090584; Invention DESIGN FOR TESTABILITY CIRCUITRY PLACEMENT WITHIN AN INTEGRATED CIRCUIT DESIGN; Applicant Synopsys, Inc.; Status Patented Case.
  • 2022-12-28: Application 18147146; Invention PERFORMING TIME-EFFICIENT CLOCK ENGINEERING CHANGE ORDERS (ECO); Applicant Synopsys, Inc.; Status Patented Case.
  • 2022-12-23: Application 18146026; Invention USING MULTIPLE ERROR CORRECTION CODE DECODERS TO STORE EXTRA DATA IN A MEMORY SYSTEM; Applicant Synopsys, Inc.; Status Patented Case.
  • 2022-12-23: Application 18088195; Invention MASK RULE CHECKING FOR CURVILINEAR MASKS FOR ELECTRONIC CIRCUITS; Applicant Synopsys, Inc.; Status Patented Case.
FiledApplicationInventionApplicantStatusGrantedPatentPublished asInventor nameInventor countryExaminer
2022-12-2918090584DESIGN FOR TESTABILITY CIRCUITRY PLACEMENT WITHIN AN INTEGRATED CIRCUIT DESIGNSynopsys, Inc.Patented Case2026-06-3012670305US20230205960A1
Farasoa Nathalie ETONO
Rajeev MURGAI
Daniel Eugenio DURÁN
Manoj GUPTA
Suryanarayana DUGGIRALA
Menno Ewout VERBEEK
Tihomir SOKCEVIC
France
India
Chile
India
United States
Netherlands
Chile
AISAKA, BRYCE M
2022-12-2818147146PERFORMING TIME-EFFICIENT CLOCK ENGINEERING CHANGE ORDERS (ECO)Synopsys, Inc.Patented Case2026-01-2712536363
Meng-Fan Wu
Taiwan
KIK, PHALLAKA
2022-12-2318146026USING MULTIPLE ERROR CORRECTION CODE DECODERS TO STORE EXTRA DATA IN A MEMORY SYSTEMSynopsys, Inc.Patented Case2024-09-1712095474
Jun Zhu
Biswanath Tayenjam
United States
India
RIZK, SAMIR WADIE
2022-12-2318088195MASK RULE CHECKING FOR CURVILINEAR MASKS FOR ELECTRONIC CIRCUITSSynopsys, Inc.Patented Case2023-09-0511748553US20230129457A1
Thomas Christopher Cecil
United States
LEE, ERIC D
2022-12-2218087731GLITCH FILTER WITH RESET CIRCUITSynopsys, Inc.Patented Case2024-10-1512119827US20240213968A1
Kailash KUMAR
Prateek SINGH
Akhil THOTLI
Sriram Kumar JAYANTHI
Rahul GUPTA
India
India
India
India
India
KIM, JUNG H
2022-12-2218087124PERFORMANCE AND THROUGHPUT WHEN MODELING HALF CYCLE PATHS DURING EMULATION OR PROTOTYPINGSynopsys, Inc.Patented Case2026-06-2312664341
Alexander Rabinovitch
Cedric Jean Alquier
Prashant Saxena
Sivaprasad Acharaya
United States
France
United States
Singapore
PARIHAR, SUCHIN
2022-12-2118086423SRAM Non-Clamping Write Driver with Write AssistSynopsys, Inc.Patented Case2024-12-1012165738US20230206970A1
Harold Pilo
United States
TRAN, MICHAEL THANH
2022-12-1918084316UNIVERSAL SERIAL BUS SCHEDULING USING REAL TIME DATASynopsys, Inc.Patented Case2024-04-0211947480US20230195670A1
Saleem Chisty MOHAMMAD
United States
DANG, PHONG H
2022-12-1918068371EXTENDED REGULAR EXPRESSION MATCHING IN A DIRECTED ACYCLIC GRAPH BY USING ASSERTION SIMULATIONSynopsys, Inc.Patented Case2026-08-2512717997US20230214574A1
Dmitry Korchemny
Israel
PARIHAR, SUCHIN
2022-12-1318080594SLACK BUDGETING AND DISCRETIZATION FOR A PROGRAMMABLE DEVICESynopsys, Inc.Patented Case2026-04-2812614013US20230186006A1
Yu-Hsuan SU
Li-En HSU
Chuan-Chia HUANG
Chien-Hung CHEN
Chia-Chi HUANG
Selma Bergaoui BEN JRAD
Taiwan
Taiwan
Taiwan
Taiwan
United States
France
PARIHAR, SUCHIN
2022-12-1218064734AUTOMATIC TEST PATTERN GENERATION TO INCREASE COVERAGE IN DETECTING DEFECTS IN ANALOG CIRCUITSSynopsys, Inc.Patented Case2026-05-1212626043US20240193336A1
Peilin Jiang
Mayukh Bhattacharya
United States
United States
NGUYEN, NHA T
2022-12-0718076981AUTOMATIC TRACKING FOR CLOCK SYNCHRONIZATION BASED ON DELAY LINE ADJUSTMENTSynopsys, Inc.Patented Case2024-07-3012051481
David Lin
Kuan Zhou
United States
United States
STOYNOV, STEFAN
2022-12-0718062773DETERMINING AGING EFFECTS FOR A CIRCUIT DESIGNSynopsys, Inc.Patented Case2026-06-1612657363US20230359796A1
Wei-Kai SHIH
Hsien-Han CHENG
Li DING
Taiwan
Taiwan
United States
AISAKA, BRYCE M
2022-12-0618076007CREATION OF REDUCED FORMAL MODEL FOR SCALABLE SYSTEM-ON-CHIP (SOC) LEVEL CONNECTIVITY VERIFICATIONSynopsys, Inc.Patented Case2026-06-0212645856US20230177244A1
Prasun Das
Pratik Mahajan
Alfred Koelbl
Henna Arora
India
United States
United States
India
PARIHAR, SUCHIN
2022-12-0518075292SIMULTANEOUS MULTI-SCENARIO STATIC NOISE ANALYSISSynopsys, Inc.Patented Case2026-01-0612518077
Peivand Tehrani
Paul Berevoescu
Shaun Koruthu Peter
United States
United States
United States
BOWERS, BRANDON
2022-12-0518074682Machine-Learning Model for Circuit Design Requirements VerificationSynopsys, Inc.Patented Case2026-04-0712596858
Tanu Aneja
Nusrat Ali
Apoorva Mathur
Jitendra Puri
India
India
India
India
PARIHAR, SUCHIN
2022-12-0118073100EVENT-DRIVEN TRACING IN STATIC TIMING ANALYSIS OF DIGITAL CIRCUIT DESIGNSSynopsys, Inc.Patented Case2025-12-2312505271US20250190664A1
Jacob Philip THOMAS
Paul GROSS
Norbert HEINDL
Clayton MCDONALD
United States
United States
United States
United States
BOWERS, BRANDON
2022-11-3018072590LOW-POWER MULTI-VARIABLE FEEDBACK CONTROL LOOPSynopsys, Inc.Patented Case2025-09-0912413383
David Edgar Castle
United States
TSE, YOUNG TOI
2022-11-3018060464PAY-PER-USE METERING SERVICE FOR ELECTRONIC DESIGN AUTOMATION WORKLOADS IN THE CLOUDSynopsys, Inc.Patented Case2025-05-2712314350
Gurbir Singh
Rajendra Rao Kundapur
Jagadeeswara R. Mandla
Shekhar Y. Mahajan
United States
United States
United States
India
KEEHN, RICHARD G
2022-11-3018060390COMBINED GLOBAL AND LOCAL PROCESS VARIATION MODELINGSynopsys, Inc.Patented Case2025-09-3012430486
Wenwen Chai
Li Ding
United States
United States
KIK, PHALLAKA
2022-11-2918071321ONE-TIME PROGRAMMABLE BITCELL FOR FRONTSIDE AND BACKSIDE POWER INTERCONNECTSynopsys, Inc.Patented Case2025-02-0412217809US20230187003A1
Andrew Edward Horch
United States
NGUYEN, HIEN N
2022-11-2918071080MEASURING DEVICE DEFECT SENSITIZATION IN TRANSISTOR-LEVEL CIRCUITSSynopsys, Inc.Patented Case2025-06-1712332301US20240061035A1
Mayukh BHATTACHARYA
Jonti TALUKDAR
Shan YUAN
Huiping HUANG
United States
United States
United States
United States
NGUYEN, NHA T
2022-11-2318058614PATTERN-BASED HIERARCHY EXPLORATION FOR COMPRESSING AN INTEGRATED CIRCUIT DESIGN LAYOUTSynopsys, Inc.Patented Case2026-07-2112687773
Yuan He
Joshua P. Tuttle
Lin Wang
Yongdong Wang
United States
United States
United States
United States
NGO, BRIAN
2022-11-2117991780APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC) SYNTHESIS BASED ON LOOKUP TABLE (LUT) MAPPING AND OPTIMIZATIONSynopsys, Inc.Patented Case2026-04-2112608523
Walter Lau Neto
Luca Gaetano Amaru
Vinicius Neves Possani
Patrick Vuillod
Jiong Luo
United States
United States
United States
France
United States
GARBOWSKI, LEIGH M
2022-11-1617988317SOLVING MULTIPLE ARRAY PROBLEMS INTERACTING WITH EACH OTHER IN CONSTRAINT SOLVING FOR FUNCTIONAL VERIFICATION OF LOGIC DESIGNSSynopsys, Inc.Patented Case2025-11-1812475285
In-Ho Moon
Qiang Qiang
United States
United States
DOAN, NGHIA M
2022-11-1517987123PERFORMING AUTOMATIC SIGN-OFF FOR CLOCK GATING VERIFICATION USING TOGGLE COVER PROPERTIESSynopsys, Inc.Patented Case2025-11-2512481814
Nishant Chauhan
Sudipta Kundu
Hanish Singla
India
United States
India
KIK, PHALLAKA
2022-11-1017985008Mask Synthesis Integrating Mask Fabrication Effects and Wafer Lithography EffectsSynopsys, Inc.Patented Case2025-11-1812474634US20230152683A1
Peng Liu
United States
DOAN, NGHIA M
2022-11-0717982043CONTROL OF LOW-POWER CHECKERS USING ASSERTION CONTROL TECHNIQUES OF ASSERTIONS LANGUAGESynopsys, Inc.Patented Case2026-02-1012547814
Subhrajyoti Chakraborty
Harsh Chilwal
Debraj Dutta
Vishal Rathi
India
United States
United States
United States
TAT, BINH C
2022-11-0417981185DESIGN OF STACKED NANOSHEET DEVICE FOR PROCESS AND PERFORMANCE OPTIMIZATIONSynopsys, Inc.Patented Case2025-10-2112453129
Xi-Wei Lin
Victor Moroz
Zudian Qin
Plamen Asenov Asenov
United States
United States
United States
United Kingdom
LEE, CHEUNG
2022-11-0417980824TRANSCEIVER DEVICES WITH TRANSMITTER AND RECEIVER FREQUENCY CONTROLSynopsys, Inc.Patented Case2025-11-2512483378US20230141608A1
Gopal Krishna Ullal NAYAK
Sanket Sanjay NAIK
Ankit SOMANI
Biman CHATTOPADHYAY
Ravi Jitendra MEHTA
Sujoy CHAKRAVARTY
Ameer Muhammad YOUSSEF
Ayal S. SHOVAL
John T. STONICK
Michael W. LYNCH
Adam Ross BURNS
India
India
India
India
India
India
Canada
Canada
United States
Canada
Canada
HO, DUC CHI
2022-10-3117977809DELAY CALCULATION WITH PATTERN MATCHING FOR STATIC TIMING ANALYSISSynopsys, Inc.Patented Case2026-08-2512717991US20240143878A1
Peivand Tehrani
Chenwei Dustin Liu
Ahmed Shebaita
United States
United States
United States
GARBOWSKI, LEIGH M
2022-10-3117977803HIGH-VOLTAGE TOLERANT MULTIPLEXERSynopsys, Inc.Patented Case2024-08-2712074593
Stephen Yue
Raymond Tam
Canada
Canada
WELLS, KENNETH B
2022-10-3117977599EMBEDDED MEMORY TRANSPARENT IN-SYSTEM BUILT-IN SELF-TESTSynopsys, Inc.Patented Case2024-06-0412002530US20230140090A1
Grigor TSHAGHARYAN
Gurgen HARUTYUNYAN
Samvel SHOUKOURIAN
Yervant ZORIAN
Armenia
Armenia
Armenia
United States
AHMED, ENAM
2022-10-2818050822HIGH BANDWIDTH INTEGRATED MULTIPLEXER AND DRIVER STAGE FOR TRANSMITTERSynopsys, Inc.Patented Case2024-06-0412003233
Varun Kant Tripathi
Shourya Kansal
India
India
NGUYEN, LONG T
2022-10-2817976723MAXIMIZING DETECTABLE DEFECT COVERAGE OF ANALOG CIRCUITS IN INTEGRATED CIRCUIT DESIGNSynopsys, Inc.Patented Case2026-01-2012530515
Mayukh BHATTACHARYA
Huiping HUANG
Mihir SHERLEKAR
Michael DURR
United States
United States
United States
United States
TAT, BINH C
2022-10-2817976720TWO-STEP DUTY-CYCLE CORRECTION FOR HIGH-SPEED CLOCKS IN COMMUNICATIONS SYSTEMSSynopsys, Inc.Patented Case2024-04-0211949421
Lukasz HABLÜTZEL
Krzysztof Woronowicz
Poland
Poland
COX, CASSANDRA F
2022-10-2718050187PARAMETERIZED SUPERCONDUCTING MULTI-ROW CIRCUITSynopsys, Inc.Patented Case2024-04-3011973497
Jamil Kawa
Stephen Robert Whiteley
Eric M. Mlinar
United States
United States
United States
O NEILL, PATRICK
2022-10-2717974888VARIED VALIDITY BIT PLACEMENT IN TAG BITS OF A MEMORYSynopsys, Inc.Patented Case2024-07-0212026094US20240143503A1
Karthik THUCANAKKENPALAYAM SUNDARARAJAN
United States
YU, JAE UN
2022-10-2717974881MEMORY COHERENCE PROTOCOL FOR COMMUNICATING DATA ASSOCIATED WITH A SHARED STATE BETWEEN PROCESSOR CORESSynopsys, Inc.Patented Case2025-05-0612292832US20240143506A1
Karthik THUCANAKKENPALAYAM SUNDARARAJAN
United States
SIMONETTI, NICHOLAS J
2022-10-2617974412COMPUTATION OF WEAKLY CONNECTED COMPONENTS IN A PARALLEL, SCALABLE AND DETERMINISTIC MANNERSynopsys, Inc.Patented Case2025-11-1812474976US20230126888A1
Olivier Rene Coudert
Krishanu Debnath
United States
India
ALAM, MOHAMMED
2022-10-2518049580PREDICTING ALIASING BITS IN A VIRTUALLY INDEXED PHYSICALLY TAGGED CACHESynopsys, Inc.Patented Case2024-10-2212124375
Karthik Thucanakkenpalayam Sundararajan
United States
UNELUS, ERNEST
2022-10-2417972318SECURED COMPUTER MEMORYSynopsys, Inc.Patented Case2025-08-1212387011US20240135040A1
Adrianus WPGG VAASSEN
Netherlands
MOORTHY, ARAVIND K
2022-10-1918047977DETERMINING A DENSITY OF THROUGH-SILICON VIAS IN INTEGRATED CIRCUITSSynopsys, Inc.Patented Case2025-12-0212489021
I-Jye Lin
Gary K. Yeap
Taiwan
United States
MENZ, LAURA MARY
2022-10-1918047922PERFORMING TIMING CONSTRAINT EQUIVALENCE CHECKING ON CIRCUIT DESIGNSSynopsys, Inc.Patented Case2025-12-0212488169
Subramanyam Sripada
Gowrishankar N. J.
Shubhashish Rudra
Ajit Sequeira
United States
India
India
India
KIK, PHALLAKA
2022-10-1917969423Aggregating Multiple Component Metrics into A Single Reward FunctionSynopsys, Inc.Patented Case2025-08-1212387025
Amzie Allen Adams
Joseph Robb Walston
United States
United States
GARBOWSKI, LEIGH M
2022-10-1917969161LINE DRIVER WITH HIGH OVER-VOLTAGE PROTECTIONSynopsys, Inc.Patented Case2025-02-0412218662
Tigran Petrosyan
Arshavir Matevosyan
Davit Vanetsyan
Davit Petrosyan
Ashot Muradyan
Armenia
United States
Armenia
Canada
Armenia
O TOOLE, COLLEEN J
2022-10-1718047237VOLTAGE SCALABLE LEVEL SHIFTERSynopsys, Inc.Patented Case2026-03-3112592682
Sayan ADHIKARY
Ankit AGRAWAL
India
India
O TOOLE, COLLEEN J
2022-10-1417966680POWER SUPPLY TRACKING CIRCUITRY FOR EMBEDDED MEMORIESSynopsys, Inc.Patented Case2024-09-1712094513US20230125268A1
Harold PILO
Shishir KUMAR
Anurag GARG
United States
India
United States
HIDALGO, FERNANDO N
2022-10-1217964742MEMORY PROFILER FOR EMULATIONSynopsys, Inc.Patented Case2025-04-0112265122
Prashant Kumar Mishra
Kiran Lokhande
Mikhail Bershteyn
Srivatsan Raghavan
India
India
United States
India
ALSHACK, OSMAN M
2022-10-1117963599MODIFYING SCAN PATTERNS TO ENABLE BROADCASTING A SCAN ENABLE SIGNAL TO MULTIPLE CIRCUIT BLOCKSSynopsys, Inc.Patented Case2025-09-0212406122
Amit Gopal M. Purohit
Denis Martin
Paras Chhabra
India
United States
India
KIK, PHALLAKA
2022-10-1017962683CONFLICT DETECTION AND ADDRESS ARBITRATION FOR ROUTING SCATTER AND GATHER TRANSACTIONS FOR A MEMORY BANKSynopsys, Inc.Patented Case2025-05-2712314572US20240118811A1
Karthik THUCANAKKENPALAYAM SUNDARARAJAN
United States
BUI, THA-O H
2022-10-0717962345LOGIC VERIFICATION OF SUPERCONDUCTING ELECTRONIC CIRCUITS, INCLUDING FOR MARGIN ANALYSIS OF YIELDSynopsys, Inc.Patented Case2026-04-2112608524
Aaron John Barker
United States
AISAKA, BRYCE M
2022-10-0717962232CONVERSION OF A CLEAN UNIQUE REQUEST TO A READ UNIQUE REQUEST BY A MEMORY COHERENCY MANAGER CIRCUITSynopsys, Inc.Patented Case2024-07-2312045167US20240119004A1
Karthik THUCANAKKENPALAYAM SUNDARARAJAN
United States
TSUI, DANIEL D
2022-10-0617961473MANAGEMENT CIRCUITRY FOR A LEAST RECENTLY USED MEMORY MANAGEMENT PROCESSSynopsys, Inc.Patented Case2024-10-2212124379US20240119007A1
Karthik THUCANAKKENPALAYAM SUNDARARAJAN
United States
PAPERNO, NICHOLAS A
2022-10-0617961415UNIFIED FRAMEWORK AND METHOD FOR ACCURATE CONTEXT-AWARE TIMING MODELINGSynopsys, Inc.Patented Case2026-08-0412699828US20230110560A1
Ruijing Shen
Li Ding
United States
United States
NGUYEN, NHA T
2022-10-0417959833MULTI-PROTOCOL ANALOG FRONT END CIRCUITSynopsys, Inc.Patented Case2025-03-1112249394US20230111161A1
Xiao YUN
Vladimir ZLATKOVIC
United States
United States
HUANG, MIN
2022-10-0317958994MANAGING HIGH PERFORMANCE SIMULATION REPRESENTATION OF AN EMULATION SYSTEMSynopsys, Inc.Patented Case2025-03-2512259806US20240111660A1
Ribhu Mittal
Deepak Kumar
United States
United States
WU, JUNCHUN
2022-09-3017937206DISTRIBUTED TEST PATTERN GENERATION AND SYNCHRONIZATIONSynopsys, Inc.Patented Case2025-06-0312320839US20240110973A1
Peter Wohl
Khader Abdel-Hafez
Michael Dylan Dsouza
United States
United States
United States
ZHANG, HAIDONG
2022-09-2917956597AUTOMATIC GLOBAL CLOCK TREE SYNTHESISSynopsys, Inc.Patented Case2023-12-0511836000
Partha Das
Tao Lin
Min Pan
United States
United States
United States
JAGER, RYAN C
2022-09-2917956550MASK FABRICATION EFFECTS IN THREE-DIMENSIONAL MASK SIMULATIONS USING FEATURE IMAGESSynopsys, Inc.Patented Case2026-05-1912631956US20230104510A1
Peng Liu
United States
GARBOWSKI, LEIGH M
2022-09-2917956034STORE INSTRUCTION MERGING WITH PATTERN DETECTIONSynopsys, Inc.Patented Case2025-05-1312299448US20240111537A1
Karthik THUCANAKKENPALAYAM SUNDARARAJAN
United States
ALLI, KASIM A
2022-09-2917955790Reducing Memory Device Bitline LeakageSynopsys, Inc.Patented Case2025-07-0812354656US20240038300A1
Shishir Kumar
Vinay Kumar
India
India
HO, HOAI V
2022-09-2817955418ENERGY EFFICIENT TAG PARTITIONING IN CACHE MEMORYSynopsys, Inc.Patented Case2024-02-1311899586
Karthik Thucanakkenpalayam Sundararajan
United States
BANSAL, GURTEJ
2022-09-2817955117GRAPH REPRESENTATION OF A CIRCUIT SIMULATION WAVEFORMSynopsys, Inc.Patented Case2026-02-0312541629US20240104278A1
Geetesh MORE
Zeng CHENG
Canada
Canada
AISAKA, BRYCE M
2022-09-2717954159MULTICYCLE PATH PREDICTION OF RESET SIGNALSSynopsys, Inc.Patented Case2025-09-0212406120US20240104279A1
Baijayanta RAY
Alexander RABINOVITCH
Manish SHROFF
India
United States
United States
KIK, PHALLAKA
2022-09-2717953689EARLY DETECTION OF SINGLE BIT ERROR ON ADDRESS AND DATASynopsys, Inc.Patented Case2025-01-0712191885
Karthik Thucanakkenpalayam Sundararajan
Geogy Jacob
United States
United States
HOSSAIN, SAZZAD
2022-09-2617953192Deterministic Cross-Platform Circuit Design EmulationSynopsys, Inc.Patented Case2026-01-2712536354
Boris Gommershtadt
Yan Zucker
Yuval Szwarcfiter
Israel
Israel
Israel
ALAM, MOHAMMED
2022-09-2617953110PLACING HARD MACROS USING MACHINE LEARNING PREDICTIONS TRAINED ON DIFFERENT CIRCUIT DESIGNSSynopsys, Inc.Patented Case2025-10-1412443785
Yi-Min Jiang
Xiang Gao
Lixin Shao
Pedja Raspopovic
United States
United States
United States
United States
DINH, PAUL
2022-09-2317951840Associating Physical Design Metrics of a Circuit Design with Register Transfer Level Representations of the Circuit DesignSynopsys, IncPatented Case2026-05-1212626039
Balkrishna Ramchandra Rashingkar
Andrew Saunders
Douglas Chang
Jeffrey Jude Loescher
Oliver Werner Kozber
Liang Tao
Soumitra Majumder
Colin Williams
United States
United Kingdom
United States
United States
United States
United States
India
United States
ALAM, MOHAMMED
2022-09-2317951528BUFFER CIRCUITRY FOR STORE TO LOAD FORWARDINGSynopsys, Inc.Patented Case2024-11-1912147707US20240103761A1
Karthik THUCANAKKENPALAYAM SUNDARARAJAN
United States
TSAI, SHENG JEN
2022-09-1617946642FUNCTIONAL SAFETY MECHANISMS FOR INPUT/OUTPUT (IO) CELLSSynopsys, Inc.Patented Case2026-01-1312524589US20230098071A1
Shivakumar Shankar Chonnad
Vladimir Litovtchenko
Sowjanya Syamala
Nidhi Bhasin
United States
Germany
India
India
NGO, BRIAN
2022-09-1617946085BUILT-IN SELF-TEST CIRCUIT FOR ROW HAMMERING IN MEMORYSynopsys, Inc.Patented Case2025-04-0112266413US20240096435A1
Grigor TSHAGHARYAN
Gurgen HARUTYUNYAN
Arun KUMAR
Yervant ZORIAN
Armenia
Armenia
United States
United States
HUR, JUNG H
2022-09-1317943712VERIFICATION OF ETHERNET HARDWARE BASED ON CHECKSUM CORRECTION WITH CYCLIC REDUNDANCY CHECKSynopsys, Inc.Patented Case2024-05-0711979232US20230086197A1
Jishnu De
Jaspreet Singh Gambhir
India
India
KABIR, ENAMUL MD
2022-09-0917942003OPTICAL PATH TRACING IN AN OPTICAL CIRCUIT DESIGNSynopsys, Inc.Patented Case2026-02-0312541097US20230083003A1
Remco STOFFER
Teunis DUBBINK
Netherlands
Netherlands
ALAM, MOHAMMED
2022-09-0717939324SELF-RECOVERY MECHANISM FOR MULTI-HOSTS AND MULTI-DEVICES EMULATION AND PROTOTYPING SYSTEM BUSSynopsys, Inc.Patented Case2024-07-0912032510
He Yin
Goichiro Ono
Zhe Zhao
Yuchen Xu
United States
United States
China
United States
YIMER, GETENTE A
2022-09-0617903925TRACE BUFFER DATA MANAGEMENT FOR EMULATION SYSTEMSSynopsys, Inc.Patented Case2025-05-2012306732US20230074456A1
Chia-Wei Liang
Wenxin Wang
Meng-Tse Chen
Goichiro Ono
Zhe Zhao
Yang Song
Yu Sui
Yuchen Xu
United States
United States
Taiwan
United States
China
United States
United States
United States
SCHELL, JOSEPH O
2022-09-0117901074ACCELERATING STATIC PROGRAM ANALYSIS WITH SUMMARY REUSESynopsys, Inc.Patented Case2024-09-1712093163
Marc-André Laverdière-Papineau
Kenneth Robert Block
Nebojsa Bozovic
Simon Fredrick Vicente Goldsmith
Charles-Henri Marie Jacques Gros
Thomas Henry Hildebrandt
Thierry M. Lavoie
Ryan Edward Ulch
Canada
United States
Canada
United States
United States
United States
Canada
Canada
RAMPURIA, SATISH
2022-09-0117901071ACCELERATING STATIC PROGRAM ANALYSIS WITH ARTIFACT REUSESynopsys, Inc.Patented Case2024-03-2611941379
Marc-André Laverdière-Papineau
Kenneth Robert Block
Nebojsa Bozovic
Simon Fredrick Vicente Goldsmith
Charles-Henri Marie Jacques Gros
Thomas Henry Hildebrandt
Thierry M. Lavoie
Ryan Edward Ulch
Canada
United States
Canada
United States
United States
United States
Canada
Canada
WANG, RONGFA PHILIP
2022-08-3117900654SELECTION AND PLACEMENT OF SAFETY MECHANISMSSynopsys, Inc.Patented Case2025-08-2612400062US20240070367A1
Shivakumar Shankar CHONNAD
United States
DINH, PAUL
2022-08-3117900427FAIL-SAFE PROTECTION ARCHITECTURE FOR HIGH VOLTAGE TOLERANT INPUT/OUTPUT CIRCUITSynopsys, Inc.Patented Case2024-08-2712074597US20240072803A1
Kailash Kumar
Prateek Singh
Akhil Thotli
India
India
India
RICHARDSON, JANY
2022-08-2917897529MASK CORNER ROUNDING EFFECTS IN THREE-DIMENSIONAL MASK SIMULATIONS USING FEATURE IMAGESSynopsys, Inc.Patented Case2025-11-2512481213US20230079453A1
Peng Liu
United States
ALAM, MOHAMMED
2022-08-2617897085DETECTING SIMULATION, EMULATION AND PROTOTYPING ISSUES USING STATIC ANALYSIS TOOLSSynopsys, Inc.Patented Case2025-05-2012307179US20230071521A1
Mohan Mangal
Rohit Kumar Ohlayan
Himanshu Kathuria
Jaskaran Singh Ajimal
United States
India
United States
India
GARBOWSKI, LEIGH M
2022-08-2617896996CONFIGURABLE, HIGH SPEED AND HIGH VOLTAGE TOLERANT OUTPUT DRIVERSynopsys, Inc.Patented Case2025-02-2512237004
Yamin Du
Vladimir Zlatkovic
Alex Alexeyev
De Zhong Cheng
Canada
United States
United States
Canada
BEGUM, SULTANA
2022-08-2617896971ATOMIC CORRECTION OF SINGLE BIT ERRORS WITHIN A MEMORYSynopsys, Inc.Patented Case2024-03-1211928024US20240070019A1
Karthik THUCANAKKENPALAYAM SUNDARARAJAN
United States
NGUYEN, THIEN DANG
2022-08-2417894557MEMORY OPTIMIZATION FOR STORING OBJECTS IN NESTED HASH MAPS USED IN ELECTRONIC DESIGN AUTOMATION SYSTEMSSynopsys, Inc.Patented Case2024-07-0212026202US20230065867A1
Brijesh Agrawal
Abhishek Verma
Deepak Ahuja
Paras Mal Jain
India
India
India
United States
TRAN, LOC
2022-08-1917891395MEMORY CLOCK LEVEL-SHIFTING BUFFER WITH EXTENDED RANGESynopsys, Inc.Patented Case2024-08-2712073876US20240062810A1
Harold Pilo
United States
BUI, THA-O H
2022-08-1717889903ROUTING OF HIGH-SPEED, HIGH-THROUGHPUT INTERCONNECTS IN INTEGRATED CIRCUITSSynopsys, Inc.Patented Case2025-08-2612400064US20230061120A1
Xun Liu
Jennifer Song Yon Pyon
United States
United States
LEE, ERIC D
2022-08-1617888974Low-Area, Wide Range Clocking Scheme using Inductance/Capacitance OscillatorsSynopsys, Inc.Patented Case2025-01-2812212308US20230063149A1
Srirup Bagchi
Kumail Khurram
United States
United States
LIAO, HSINCHUN
2022-08-1017885386CLOCK MULTIPLEXER CIRCUITRY WITH GLITCH REDUCTIONSynopsys, Inc.Patented Case2023-11-2111824539US20230051554A1
Hardik ARORA
Amit VERMA
Basannagouda Somanath REDDY
India
India
Canada
JAGER, RYAN C
2022-08-0817883357ACCOUNTING FOR STEADY STATE NOISE IN BIT RESPONSE SUPERPOSITION BASED EYE DIAGRAM SIMULATIONSynopsys, Inc.Patented Case2025-07-0812353813US20230066423A1
Tetsuhisa MIDO
Japan
KIK, PHALLAKA
2022-08-0417881526MULTI-MACHINE VERSION INDEPENDENT HIERARCHICAL VERIFICATIONSynopsys, Inc.Patented Case2025-11-2512481812
Anchit Jain
Deepak Ahuja
Paras Mal Jain
Pronay Kumar Biswas
Abhinav Singla
India
India
United States
United States
India
KIK, PHALLAKA
2022-08-0217879571PARTITIONING A CIRCUIT FOR DISTRIBUTED BALANCED INDEPENDENT SIMULATION JOBS WITH UPPER-BOUNDED MEMORYSYNOPSYS, INC.Patented Case2025-05-0612293139
Olivier COUDERT
Tien-Chien LEE
Songra PAN
Suman NANDAN
United States
United States
United States
United States
LEE, ERIC D
2022-07-2917877266GENERATING AND UTILIZING MANUFACTURABLE NETLISTS OF THREE-DIMENSIONAL INTEGRATED CIRCUITSSynopsys, Inc.Patented Case2025-09-0212406117
Xun Liu
United States
KIK, PHALLAKA
2022-07-2817876446OVERLAPPED INDUCTOR STRUCTURESynopsys, Inc.Patented Case2026-05-0512620520US20230042967A1
Jayesh WADEKAR
Jayashankar MV
Jairaj NAIK K R
Atul KABRA
India
India
India
India
BREENE, JOHN E
2022-07-2717875228METHOD AND SYSTEM FOR TRANSMISSION POWER CONTROL IN BLUETOOTH LOW ENERGY CONTROLLERSSynopsys, Inc.Patented Case2025-03-0412245163
Khaled M.F. Elsayed
Egypt
REGO, DOMINIC E
2022-07-2517873015BOUNDARY CELL HAVING A COMMON SEMICONDUCTOR TYPE FOR LIBRARY CELLSynopsys, Inc.Patented Case2026-01-2712536360US20230022615A1
Arpit JAIN
India
LEE, ERIC D
2022-07-2117870562UNWANTED PEAK REDUCTION IN EQUALIZERSynopsys, Inc.Patented Case2024-01-0211863170
Jayesh WADEKAR
Jairaj NAIK K R
Atul KABRA
India
India
India
NGUYEN, LONG T
2022-07-2117870381WAVEFORM CAPTURE USING MULTICYCLE PATH PROPERTIESSynopsys, Inc.Patented Case2025-12-0212488177US20240028812A1
Alexander RABINOVITCH
Baijayanta RAY
United States
India
TAT, BINH C
2022-07-2117870374CLOCK SIGNAL REALIGNMENT FOR EMULATION OF A CIRCUIT DESIGNSynopsys, Inc.Patented Case2025-11-1112468334US20230035693A1
Alexander RABINOVITCH
Manish SHROFF
Baijayanta RAY
United States
United States
India
KIK, PHALLAKA
2022-07-1917868325UNIFIED POWER FORMAT ANNOTATED RTL IMAGE RECOGNITION TO ACCELERATE LOW POWER VERIFICATION CONVERGENCESynopsys, Inc.Patented Case2025-07-0812353810US20230043751A1
Zamrath NIZAM
Chirath Chamikara DIYAGAMA
Bhaskar PAL
Ashan WICKRAMASINGHE
Sri Lanka
Sri Lanka
United States
Sri Lanka
KIK, PHALLAKA

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