SYNOPSYS INC Patent Applications Pending
929 applications still open at the USPTO, newest filing first, as the USPTO Open Data Portal records them; the company is the first-named applicant. The application number opens the full record at Patent Center.
- 2025-11-24: Application 19399603; Invention DIVIDING A CHIP DESIGN FLOW INTO SUB-STEPS USING MACHINE LEARNING; Applicant Synopsys, Inc.; Status Docketed New Case - Ready for Examination.
- 2025-11-10: Application PCTUS2025054836; Invention MACHINE-LEARNING-AIDED LOGIC SYNTHESIS USING DO-NOT-CARE-BASED BACKPROPAGATION; Applicant SYNOPSYS, INC.; Status RO PROCESSING COMPLETED-PLACED IN STORAGE.
- 2025-10-10: Application PCTUS2025050600; Invention GRAPH-BASED VISUALIZATION OF WAYPOINT FOR DETECTING DESIGN ERROR IN INTEGRATED CIRCUIT DESIGN; Applicant SYNOPSYS, INC.; Status RO PROCESSING COMPLETED-PLACED IN STORAGE.
- 2025-08-25: Application 19308726; Invention METHODS AND SYSTEMS FOR THE ESTIMATION OF THE COMPUTATIONAL COST OF SIMULATION; Applicant Synopsys, Inc.; Status Docketed New Case - Ready for Examination.
| Filed | Application | Invention | Applicant | Status | Published as | Inventor name | Inventor country | Examiner |
|---|---|---|---|---|---|---|---|---|
| 2025-11-24 | 19399603 | DIVIDING A CHIP DESIGN FLOW INTO SUB-STEPS USING MACHINE LEARNING | Synopsys, Inc. | Docketed New Case - Ready for Examination | US20260080143A1 | Amzie Allen Adams Joseph R. Walston Piyush Verma | United States United States United States | CENTRAL, DOCKET |
| 2025-11-10 | PCTUS2025054836 | MACHINE-LEARNING-AIDED LOGIC SYNTHESIS USING DO-NOT-CARE-BASED BACKPROPAGATION | SYNOPSYS, INC. | RO PROCESSING COMPLETED-PLACED IN STORAGE | YUKIO MIYASAKA WALTER LAU NETO PATRICK EMMANUEL VUILLOD ELEONORA TESTA ANIKA AISHWARYA PRASAD RETO ZIMMERMAN MICHAEL SHUSTER LUCA GAETANO AMARU | United States United States France United States United States Switzerland United States United States | ||
| 2025-10-10 | PCTUS2025050600 | GRAPH-BASED VISUALIZATION OF WAYPOINT FOR DETECTING DESIGN ERROR IN INTEGRATED CIRCUIT DESIGN | SYNOPSYS, INC. | RO PROCESSING COMPLETED-PLACED IN STORAGE | SUBHADIP HALDER PRASUN DAS HIMANSHU JAIN PALLAB DASGUPTA PER BJESSE | India United States United States United States United States | ||
| 2025-08-25 | 19308726 | METHODS AND SYSTEMS FOR THE ESTIMATION OF THE COMPUTATIONAL COST OF SIMULATION | Synopsys, Inc. | Docketed New Case - Ready for Examination | US20260278215A1 | Kyle Kosic Anil Sehgal Scott McClennan Joshua Oster-Morris Ryan Diestelhorst David M. Freed Ian Campbell | United States United States United States United States United States United States United States | CENTRAL, DOCKET |
| 2025-08-04 | 19290109 | MACHINE-LEARNING-AIDED LOGIC SYNTHESIS USING DO-NOT-CARE-BASED BACKPROPAGATION | Synopsys, Inc. | Docketed New Case - Ready for Examination | Yukio MIYASAKA Walter LAU NETO Patrick Emmanuel VUILLOD Eleonora TESTA Anika Aishwarya PRASAD Reto ZIMMERMAN Michael SHUSTER Luca Gaetano AMARU | United States United States France United States United States Switzerland United States United States | CENTRAL, DOCKET | |
| 2025-07-08 | 19146472 | Circuitry for Staggering Capture Clocks in Testing Electronic Circuits with Multiple Clock Domains | Synopsys, Inc. | Docketed New Case - Ready for Examination | US20260227442A1 | Bala Tarun Nelapatla Likith Kumar Manchukonda Ke Xue Mona Marie Marmash Peter Wohl | United States United States China United States United States | CENTRAL, DOCKET |
| 2025-06-25 | PCTUS2025035256 | GENERATING HARDWARE DESCRIPTION LANGUAGE SLICES TO PROVIDE CONTEXT FOR VIOLATIONS | SYNOPSYS, INC. | RO PROCESSING COMPLETED-PLACED IN STORAGE | THANUJA MADUSANKA HIMANSHU KATHURIA MOHAN MANGAL JASKARAN SINGH AJIMAL ROHIT KUMAR OHLAYAN PARAS MAL JAIN | Sri Lanka United States United States United States India United States | ||
| 2025-06-17 | 19241219 | DYNAMIC CLOCK TREE PLANNING USING FEEDTIMING COST | Synopsys, Inc. | Docketed New Case - Ready for Examination | US20250315589A1 | Vivek Kumar Prashant Gupta | India India | CENTRAL, DOCKET |
| 2025-06-04 | PCTUS2025032349 | MEMORY CELL NOISE PROTECTION VIA BIDIRECTIONAL THRESHOLD SWITCHING DEVICES | SYNOPSYS, INC. | RO PROCESSING COMPLETED-PLACED IN STORAGE | ROUWAIDA KANJ | United States | ||
| 2025-05-21 | 19214895 | MEASURING DEVICE DEFECT SENSITIZATION IN TRANSISTOR-LEVEL CIRCUITS | Synopsys, Inc. | Docketed New Case - Ready for Examination | US20250290974A1 | Mayukh BHATTACHARYA Jonti TALUKDAR Shan YUAN Huiping HUANG | United States United States United States United States | CENTRAL, DOCKET |
| 2025-05-19 | 19212337 | DISTRIBUTED TEST PATTERN GENERATION AND SYNCHRONIZATION | Synopsys, Inc. | Non Final Action Mailed | US20260160803A1 | Peter Wohl Khader Abdel-Hafez Michael Dylan Dsouza | United States United States United States | ZHANG, HAIDONG |
| 2025-04-18 | PCTUS2025025453 | VIRTUAL MACHINE EXECUTION WITH HETEROGENOUS HOST AND VIRTUAL MACHINE INSTRUCTION SET ARCHITECTURES | SYNOPSYS, INC. | RO PROCESSING COMPLETED-PLACED IN STORAGE | SIMON SCHÖNING THOMAS MICHAEL PHILIPP DIETMAR PETRAS | United States United States United States | ||
| 2025-04-16 | 19181093 | BOOLEAN REASONING GUIDED UNGROUPING ACROSS CIRCUIT DESIGN HIERARCHY | Synopsys, Inc. | Docketed New Case - Ready for Examination | US20260141147A1 | Eleonora TESTA Alan Allwyn VAZ Abhishek KUMAR Brian E. LOCKYEAR Luca Gaetano AMARU Elena TEICA Giulia MEULI Vishal F. ARALIKATTI | United States United States India United States United States United States Italy India | CENTRAL, DOCKET |
| 2025-04-16 | 19180540 | DYNAMIC RESOURCE ALLOCATION FOR COMPUTATIONAL SIMULATION | Synopsys Inc. | Docketed New Case - Ready for Examination | US20260169796A1 | Ian Campbell Ryan Diestelhorst Joshua Oster-Morris David M. Freed Scott McClennan | United States United States United States United States United States | CENTRAL, DOCKET |
| 2025-04-04 | 19170474 | SCALABLE DISTRIBUTED ENVIRONMENT FOR RESET DOMAIN CROSSING ANALYSIS AND INTERACTIVE DEBUG | Synopsys, Inc. | Docketed New Case - Ready for Examination | US20260050721A1 | Abhishek Kumar Brijesh Agrawal Anubhav Tihar Anshul Garg Sean O'Donohue Ajay Kumar | India India India India United States India | CENTRAL, DOCKET |
| 2025-03-20 | 19085257 | MEMORY DEVICE WITH IMPROVED SENSING MARGIN AND LEAKAGE IMMUNITY | Synopsys, Inc. | Docketed New Case - Ready for Examination | US20260293078A1 | Salvatore Maria Amoroso Plamen Asenov Asenov Meng-Hsuan Ke Ko-Hsin Lee Xi-Wei Lin | United Kingdom United Kingdom Taiwan Taiwan United States | CENTRAL, DOCKET |
| 2025-03-05 | 19071318 | CLOCK AWARE SIMULATION VECTOR PROCESSOR | Synopsys, Inc. | Docketed New Case - Ready for Examination | US20250238590A1 | Ramesh NARAYANASWAMY Subramanian GANESAN Dinesh Madusanke PASIKKU HANNADIGE | United States United States Sri Lanka | CENTRAL, DOCKET |
| 2025-02-14 | 19054298 | MANAGING HIGH PERFORMANCE SIMULATION REPRESENTATION OF AN EMULATION SYSTEM | Synopsys, Inc. | Docketed New Case - Ready for Examination | US20250190336A1 | Ribhu Mittal Deepak Kumar | United States United States | CENTRAL, DOCKET |
| 2025-01-31 | PCTUS2025014035 | POWER PERFORMANCE AREA OPTIMIZATION IN DESIGN TECHNOLOGY CO-OPTIMIZATION FLOWS | SYNOPSYS, INC. | RO PROCESSING COMPLETED-PLACED IN STORAGE | WENWEN CHAI LI DING | United States United States | ||
| 2025-01-17 | PCTUS2025012126 | DETECTION OF MALICIOUS CIRCUITS INSERTED IN ANALOG CIRCUITS | SYNOPSYS, INC. | RO PROCESSING COMPLETED-PLACED IN STORAGE | MAYUKH BHATTACHARYA JAYEETA CHAUDHURI KRISHNENDU CHAKRABARTY | United States United States United States |
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