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INTEGRATED SILICON SOLUTION INC Patents: Active

INTEGRATED SILICON SOLUTION INC Active Patents

10 granted patents the USPTO still lists as patented, newest filing first, as the USPTO Open Data Portal records them; the company is the first-named applicant. The application number opens the full record at Patent Center.

  • 2023-02-20: Application 18111662; Invention SEMICONDUCTOR INTEGRATED CIRCUIT; Applicant Integrated Silicon Solution Inc.; Status Patented Case.
  • 2023-02-14: Application 18168628; Invention MEMORY INTERFACE CIRCUITRY AND BUILT-IN SELF-TESTING METHOD; Applicant Integrated Silicon Solution Inc.; Status Patented Case.
  • 2023-02-02: Application 18163338; Invention METHOD OF FORMING PACKAGE STRUCTURE; Applicant Integrated Silicon Solution Inc.; Status Patented Case.
  • 2023-01-06: Application 18093817; Invention SIGNAL SYNCHRONIZATION ADJUSTMENT METHOD AND SIGNAL SYNCHRONIZATION ADJUSTMENT CIRCUIT; Applicant Integrated Silicon Solution Inc.; Status Patented Case.
FiledApplicationInventionApplicantStatusGrantedPatentPublished asInventor nameInventor countryExaminer
2023-02-2018111662SEMICONDUCTOR INTEGRATED CIRCUITIntegrated Silicon Solution Inc.Patented Case2025-02-2512237669US20240283440A1
Kang Min Lee
Kwang Kyung Lee
Seung Cheol Bae
Young Jin Yoon
Sang Min Jun
Sun Byeong Yoon
United States
United States
United States
United States
United States
United States
CLARK, CHRISTOPHER JAY
2023-02-1418168628MEMORY INTERFACE CIRCUITRY AND BUILT-IN SELF-TESTING METHODIntegrated Silicon Solution Inc.Patented Case2024-12-3112183411US20240274214A1
Hyeon Jae LEE
Jeong Ho BANG
Wol Jin LEE
Ki Hyung RYOO
Kwang Rae CHO
Sun Byeong YOON
United States
United States
United States
United States
United States
United States
LAPPAS, JASON
2023-02-0218163338METHOD OF FORMING PACKAGE STRUCTUREIntegrated Silicon Solution Inc.Patented Case2024-04-0911951571US20230173615A1
Cheng-Fu YU
Kai-Jih SHIH
Yi-Jung LIU
United States
United States
United States
NGUYEN, THANH T
2023-01-0618093817SIGNAL SYNCHRONIZATION ADJUSTMENT METHOD AND SIGNAL SYNCHRONIZATION ADJUSTMENT CIRCUITIntegrated Silicon Solution Inc.Patented Case2024-10-1512119041US20240233807A1
Sang Min Jun
Kwang Kyung Lee
Seung Cheol Bae
Kang Min Lee
Young Jin Yoon
Sun Byeong Yoon
United States
United States
United States
United States
United States
United States
TRAN, ANTHAN
2022-12-2318145927MEMORY CORE CHARACTERISTIC SCREENING METHOD AND SYSTEM THEREOFIntegrated Silicon Solution Inc.Patented Case2025-03-2512260930US20240212728A1
Jeong Ho BANG
Hyeon Jae LEE
Wol Jin LEE
Ki Hyung RYOO
Kwang Rae CHO
Sun Byeong YOON
United States
United States
United States
United States
United States
United States
NGUYEN, VIET Q
2022-11-2317992938MEMORY DEVICE HAVING ROW DRIVER CIRCUITS FOR REDUCING LEAKAGE CURRENTS DURING POWER OFFIntegrated Silicon Solution Inc.Patented Case2025-04-0112266418US20240170028A1
Youngjin Yoon
Kwang Kyung Lee
Seung Cheol Bae
Kangmin Lee
Sangmin Jun
Sun Byeong Yoon
United States
United States
United States
United States
United States
United States
CHO, SUNG IL
2022-05-0417736119CONTROLLING CIRCUIT FOR LOW-POWER LOW DROPOUT REGULATOR AND CONTROLLING METHOD THEREOFIntegrated Silicon Solution Inc.Patented Case2023-12-1211841722US20230176600A1
Shuenrun Seara JIAN
United States
JACKSON, LAKAISHA
2022-03-2517704152POWER MANAGEMENT CIRCUIT IN LOW-POWER DOUBLE DATA RATE MEMORY AND MANAGEMENT METHOD THEREOFIntegrated Silicon Solution Inc.Patented Case2024-02-0611894043US20230140988A1
Shuenrun Seara JIAN
United States
SIDDIQUE, MUSHFIQUE
2021-12-2817563214FINFET STACK GATE MEMORY AND METHOD OF FORMING THEREOFIntegrated Silicon Solution Inc.Patented Case2023-03-2811616145US20220123146A1
Hsingya Arthur WANG
United States
BRADFORD, PETER
2021-09-2917488503WAFER-BONDING STRUCTURE AND METHOD OF FORMING THEREOFIntegrated Silicon Solution Inc.Patented Case2024-06-2512021059US20220020721A1
Hsingya Arthur WANG
Sheng-Yuan CHOU
Yu-Ting WANG
Wan-Yi CHANG
United States
United States
United States
United States
JEAN BAPTISTE, WILNER