PERASO INC. (PRSO) Business

We are a fabless semiconductor company focused on the development and sale of: i) millimeter wavelength wireless technology, or mmWave, semiconductor devices and antenna modules based on our proprietary semiconductor devices and ii) performance of non-recurring engineering, or NRE, services and licensing of intellectual property, or IP. Our primary focus is the development of mmWave technology for wireless communications. mmWave is generally described as the frequency band from 24 Gigahertz, or GHz, to 300 GHz. Our mmWave products, which primarily operate in the spectrum from 24 GHz to 71 GHz, enable a range of applications including: multi-gigabit point-to-point, or PtP, wireless links with a range of up to 25 kilometers and operating in the 60 GHz frequency band; multi-gigabit point-to-multi-point, or PtMP, links in the 60 GHz frequency band used to provide fixed wireless access, or FWA, services; FWA in the 5G operating bands from 24 GHz to 43 GHz to provide multi-gigabit capability and low latency connections; military communications; and consumer applications, such as high performance wireless video streaming and untethered augmented reality and virtual reality. We also had a line of memory-denominated integrated circuits, or ICs, for high-speed cloud networking, communications, security appliance, video, monitor and test, data center and computing markets that delivered time-to-market, performance, power, area and economic benefits for system original equipment manufacturers, or OEMs. As discussed below, we initiated an end-of-life of these products in 2023, and substantially fulfilled all outstanding EOL orders of our memory IC products as of March 31, 2025.

We were formerly known as MoSys, Inc., or MoSys. On September 14, 2021, we and our subsidiaries, 2864552 Ontario Inc. and 2864555 Ontario Inc., entered into an Arrangement Agreement, or the Arrangement Agreement, with Peraso Technologies Inc., or Peraso Tech, a privately-held corporation existing under the laws of the province of Ontario, to acquire all of the issued and outstanding common shares of Peraso Tech, or the Peraso Shares, including those Peraso Shares to be issued in connection with the conversion or exchange of secured convertible debentures and common share purchase warrants of Peraso Tech, as applicable, by way of a statutory plan of arrangement, or the Arrangement, under the Business Corporations Act (Ontario). On December 17, 2021, following the satisfaction of the closing conditions set forth in the Arrangement Agreement, the Arrangement was completed, and we changed our name from MoSys to “Peraso Inc.” and began trading on The Nasdaq Stock Market, or the Nasdaq, under the symbol “PRSO.” Certain previous shareholders of Peraso Tech elected to convert their Peraso Tech common stock into exchangeable shares in 2864555 Ontario Inc., one of our wholly-owned subsidiaries. These exchangeable shares, which can be converted into our common stock at the option of the holder, are similar in substance to our common stock.

Historically, virtually all wireless communications have utilized the frequency spectrum below 6 GHz. Primary examples include cell phone communications, WiFi, Bluetooth, Internet of Things, and more recently, broadband internet access or FWA. In parallel, a broad array of applications continues to push the boundaries of available wireless network capacity. These include video streaming services, such as those offered by Netflix, Apple and Amazon, user-generated video content, such as TikTok and Instagram Reels, and broadly, personal video content generated by personal mobile devices.

While the sub-6 GHz band has traditionally been sufficient for these services, with growing demand, the mmWave spectrum is an additional source of wireless capacity. Wireless spectrum is an extremely valuable commodity and is highly regulated by federal governments around the world. Spectrum is broadly segmented into either licensed frequencies or unlicensed frequencies, although most frequencies are licensed. The mmWave frequencies between 24 GHz and 100 GHz include both licensed and unlicensed spectrum. In the case of mmWave, the 3rd Generation Partnership Project, or 3GPP, has included the spectrum from 24 GHz to 43 GHz in its 5G specification. This is licensed spectrum in most jurisdictions around the world, and carriers must license this spectrum if they choose to utilize the mmWave frequency bands within that spectrum. Alternatively, the spectrum from 57 GHz to 71 GHz is generally unlicensed around the world, and, therefore, a license is not required to operate in this spectrum. To that end, the Institute of Electrical and Electronics Engineers, or IEEE, has established two standards which utilize this unlicensed mmWave spectrum, IEEE 802.11ad and IEEE 802.11ay. We have developed silicon products that comply with both the licensed and unlicensed standards.

In an August 2024 report titled, Millimeter Wave Technology, Allied Market Research valued the global mmWave technology market at $3.4 billion, and forecasted it to grow at a 20% compound annual growth rate from 2024 to 2032.

IEEE 802.11ad/ay: License-Free mmWave Market

A primary opportunity for our mmWave products in unlicensed-band applications is the FWA market. In this market segment, wireless Internet service providers, or WISPs, provide their customers with a fixed wireless link to a base station or small cell, thus providing the customer with high-speed access to the Internet. mmWave can provide both upload and download speeds of over 1 Gbps. In addition, we believe mmWave is generally a much less expensive alternative to installing underground fiber optic cable and provides FWA carriers with competitive and cost advantages compared to other access technologies, such as cable broadband. From an equipment perspective, the FWA worldwide market has historically been serviced by OEMs, such as Ubiquiti Inc., or Ubiquiti, Cambium Networks, Ltd. and SIA MikroTik. Generally, WISPs address segments of the broadband market either not served or underserved by the traditional carriers, such as rural markets.

The FWA market has been helped in recent years with the advent of government incentives aimed at closing the so-called ‘digital divide’ between urban and rural broadband access. In 2023, the U.S. government established the Broadband Equity, Access, and Deployment, or BEAD, program, which allocated $42.45 billion to expand high-speed Internet access by funding planning, infrastructure deployment and adoption programs in all 50 states. The National Telecommunications and Information Administration, or NTIA, is the agency responsible for administering the BEAD program. When initially introduced, the NTIA had originally provided guidance that BEAD funding would be prioritized for primarily fiber deployments, and that alternative technologies such as unlicensed fixed wireless were not eligible for BEAD program funding. During 2025, the NTIA espoused a shift to a technology-neutral approach including all forms of FWA, including services enabled by our 60GHz mmWave wireless technology.

A related opportunity for us in the license-free FWA space is dense urban markets, many of which have a high saturation of informal settlements. In a December 2023 report, the International Telecommunications Union, or ITU, reported that an estimated 2.6 billion people, or one-third of the global population, does not have Internet access. As of August 2023, the World Economic Forum estimated there were over 1.1 billion people living in informal settlements around the world. Traditional last mile technology, such as WiFi, is not able to handle the congestion generated by the dense concentration of users in such communities. This is because WiFi radio signals spread out in all directions, much like a light bulb. Due to the very high population density in informal settlements, numerous WiFi transmitters are required, and as such, tend to cancel each other out with overlapping signals. Because our mmWave technology utilizes beamforming, the signals are more like beams from a car headlight, very narrow and controlled. Therefore, in a dense environment, mmWave is much better at handling high congestion, as the radio signals generally do not overlap. Another advantage our mmWave technology provides in the dense urban environment is reduced power consumption. The power grid in an informal settlement can often be unreliable. Our technology can operate under 12 watts, which enables communications networks to continue to operate on a backup battery power supply for several hours.

An additional market for our 60GHz mmWave products is military applications requiring secure communications. Specifically, as a result of our radio frequency, or RF, beamforming and beamsteering capabilities, militaries and defense contractors are evaluating the use of mmWave for stealth tactical communications. Unlike traditional wireless technology that radiates equally in all directions (omni), mmWave technology utilizes phased-array RF beams to focus the RF energy into a specific intensity and direction. The military views mmWave as an inherently stealthy protocol – Low Probability of Interception (LPI)/Low Probability of Detection (LPD)/Anti-Jamming (AJ). As the 60GHz spectrum band is generally unlicensed around the world, these communications will not interfere with locally licensed spectrum, providing additional benefit. Also, as our devices operate at under 12 watts, a light battery can be used for simple deployment in field deployments and combat settings. Further, as our mmWave technology can support gigabit speeds, military personnel are able to transmit and receive information in a timely manner. Our lead defense contractor customer is using our mmWave technology in an Identification Friend or Foe, or IFF, system designed to operate in highly contested electronic warfare environments. Our customer’s IFF system enables secure identification between and amongst ground forces and between ground forces and drones, allowing counter-drone systems and battlefield operators to determine whether aerial platforms are friendly or hostile. At the core of the customer’s system, our 60 GHz beamforming wireless transceivers provide the communications backbone for highly directional, low-power links that reduce the likelihood of detection or interception, making them well suited for dense electronic warfare environments.

Our 60 GHz products can also be applied to consumer applications, as we believe our technology can provide key advantages to this market. For example, we are targeting the high-performance, video-streaming market, specifically the virtual reality, or VR, market. Uses of VR are envisioned in a broad variety of markets, including gaming, real estate, healthcare, and transportation. We believe that our mmWave technology has certain characteristics that are ideal for VR applications. First, mmWave’s high data rate of 3 Gbps supports high-resolution displays. Second, our proprietary beamforming and beamtracking techniques keep latency to under 5 milliseconds, or ms, so the user does not experience lags. Third, mmWave technology is less susceptible to interference and, as mentioned above in the context of dense urban environments, can operate in highly congested environments, which limits interruptions in the VR user’s experience.

Other market opportunities for 60 GHz mmWave technology include transportation safety, factory automation, and railway communications.

3GPP: Licensed mmWave Market

The frequency band from 24 GHz to 43 GHz has been designated as the mmWave band in 5G communications. In the United States, this band is generally licensed to carriers by the FCC for expensive license fees that can reach billions of dollars. Carriers license this spectrum to ensure there is no interference from other carriers using the same frequencies. We believe that the primary benefit of mmWave to carriers is the availability of additional spectrum within the licensed band, to provide additional capacity to handle the growth of mobile users.

Our initial target for licensed-band applications is the FWA segment, as carriers can utilize the additional network capacity offered by mmWave to provide FWA services. According to the Ericsson Mobility Report, as of November 2023, approximately 80% of mobile service providers have an FWA offering and 121 service providers offer FWA services over 5G, representing 50% of all FWA service providers. According to Mobile Experts Inc.’s report, 5G Millimeter Wave 2023, mobile operators that have deployed 5G mmWave include Verizon, T-Mobile, AT&T, NTT DoCoMo, KDDI, Softbank and Rakuten Mobile. We believe major Chinese mobile carriers have commenced formal collaborations to advance mmWave solutions in the Chinese telecom market. Regarding U.S. carriers, FWA has become a bright spot for their 5G roll out. While U.S. carriers currently use the sub 6 GHz frequency band, eventually, as the network gets saturated, we believe the carriers will commence a broad roll out of mmWave technology. In terms of FWA market potential in the U.S., according to Fierce Wireless, T-Mobile is available to over 50 million homes, and Verizon is available to over 40 million homes. In addition to being used to provide FWA services, our mmWave antenna modules can be utilized in consumer-premises equipment or CPE, including hotspots, laptops and tablets. In its report, 5G Millimeter Wave 2023, Mobile Experts Inc. forecasts a total volume of approximately 2 million mmWave-enabled CPE units by 2026.

5G mmWave has support from major industry players, such as Apple, which has incorporated mmWave wireless into substantially all versions of the iPhone for sale in the U.S. market. The basic premise is the ever-increasing demand for bandwidth. The initial use case for cellular service providers is to provide their customer base (primarily smart-phone customers) with continuity of network access in highly congested environments, such as sporting events, public beaches, music festivals or generally any large gathering where thousands of users are attempting to access the network simultaneously. We believe that mmWave will gain universal acceptance, as users will demand full continuity in terms of network access, and we are well positioned to address the mobile opportunity for mmWave, which is expected to present an order of magnitude increase in the total available market.

Our primary focus is the development, marketing and sale of our mmWave products.

mmWave ICs

Currently, there are two industry standards that incorporate mmWave technology for wireless communications: (i) license-free: IEEE 802.11ad/ay and (ii) licensed: 3GPP Release 15-17 (commonly referred to as 5G). We have developed and continue to develop products that conform to these standards. To date, we have not sold any 5G products, as our primary business focus remains license-free markets.

Our first mmWave IC product line operates in the license-free 60 GHz band and conforms to the IEEE 802.11ad standard. This product line includes a baseband IC, several variations of mmWave radio frequency, or RF, ICs, and associated antenna technology.

Our 60 GHz IEEE802.11ad products have two very important advantages over traditional 2.4 GHz / 5 GHz Wi-Fi products: very high data rates (up to 3.0 Gbps) and low latency, i.e., less than 5 ms. The first application that had traction was outdoor broadband, including applications such as PtP backhaul links or FWA using PtMP links. As the spectrum is unlicensed (free), wireless Internet service providers, or WISPs, can provide services without having to procure expensive wireless spectrum licenses. We believe that our mmWave technology can be deployed quickly and cost effectively in rural and suburban environments, including in remote and low-income regions where residents often have poor Internet quality. While carriers can provide fiber access, the cost of fiber deployment can be prohibitive and trenching for fiber is time consuming and can limit the rate at which new subscribers are added. Our mmWave products enable WISPs to deploy broadband service using low-cost terminals and infrastructure, while avoiding the costs of deploying cable or fiber.

We are a leading supplier of semiconductors in the mmWave PtP and PtMP markets. We are currently shipping to leading equipment suppliers in this space, as well as directly to service providers that are building their own equipment. We believe we bring certain advantages to the market, including our products supporting the spectrum from 66 GHz to 71 GHz, which is often referred to as channels 5 and 6 in the 802.11ad/ay specifications. The key advantage in supporting these channels is that the signals are able to propagate much further than channels 1 through 4; this is a result of significantly lower oxygen absorption at frequencies above 66 GHz. To date, our FWA customers have achieved links in the range of 25 kilometers, which we believe is industry-leading.

In the indoor area, the 802.11ad technology is ideal for high-speed, low-latency video applications, and our products can support 3Gbps links with under 5 ms of latency. Representative applications include:

● AR/VR links between the headset and the video console;

● USB video cameras for corporate video conferencing;

● wireless security cameras; and

● smart factory safety and surveillance.

Our mmWave ICs have been in volume production since 2018. A core competency of the Company is phased-array technology, or beamforming, in which an array of antenna elements work in unison to create a focused RF beam. Through adjustment of the relative phase of the antenna signals, the beams can be directed to support robust wireless connection. We are a leader in the production of mmWave devices and have pioneered a high-volume mmWave production test methodology using standard low-cost production test equipment. It has taken us several years to refine performance of this production test methodology, and we believe this places us in a leadership position in addressing the operational challenges of delivering mmWave products into high-volume markets.

Our second product line addresses the 5G mmWave opportunity. In its 4G-5G FWA Survey 2024 issued in August 2024, the Global Mobile Supplier Association reported that 5G mmWave FWA was ramping and that shipments of 5G devices with mmWave capability are expected to grow 22% in 2024, while still representing less than 10% of all 5G device shipments. Given our extensive experience in the development of mmWave technology, 5G mmWave is a logical adjacent and larger market. We have sampled a highly integrated 5G mmWave beamformer IC, which operates in the 24 GHz to 43 GHz frequency range. The device supports dual-stream multiple input, multiple output, or MIMO, with two 16-channel beamforming arrays.

mmWave Antenna Modules

We produce and sell complete mmWave antenna modules for license-free 60 GHz applications. The primary advantage provided by our antenna modules is that our proprietary mmWave ICs and the antenna are integrated into a single device. A differentiating characteristic of mmWave technology is that the RF amplifiers must be as close as possible to the antenna to minimize loss. Our module is designed to enhance the performance of the amplifier/antenna interface and simplify customers’ RF engineering, facilitating more opportunities for customer prospects that have not provided RF-type systems, as well as shortening the time to market for new products. It is possible for third parties to provide competitive module products, but, because we utilize our mmWave ICs and incorporate our proprietary mmWave antenna IP, we can provide a highly-competitive solution based on our internally-owned and developed module components.

Our PERSPECTUS family of mmWave antenna modules enable WISPs to offer high-capacity FWA networks in the unlicensed 60-GHz spectrum. The PERSPECTUS product family includes our integrated 60 GHz mmWave antenna modules and enhanced software for PtMP FWA applications. Our PERSPECTUS products allow rapid development of low-cost network equipment utilizing over 14 GHz of spectrum to provide multi-gigabit access services. Leveraging our integrated phased-array antennas and operating in the upper channels of the band, link ranges from 1.5 kilometers up to extended ranges of 30 kilometers can be achieved using a parabolic reflector.

Additionally, we have established an innovative user arbitration protocol called DUNE that is specifically designed to optimize network performance in dense urban environments using our PERSPECTUS antenna modules. DUNE is a result of our decade-long experience in mmWave technology and in-house development of the intellectual property incorporated in media access control, which controls the hardware, the physical layer, which controls the physical connection and software drivers, as well as novel antenna designs and beamforming algorithms. DUNE takes a multi-level approach to reducing contention and interference by incorporating both physical, e.g. antenna and beamforming, and protocol-level innovations.

Memory

We had a memory product line comprising our Bandwidth Engine ICs, which are memory-denominated ICs that were designed to be i) high-performance companion ICs to packet processors and ii) targeted for high-performance applications where throughput is critical. Taiwan Semiconductor Manufacturing Corporation, or TSMC, the sole foundry that manufactured the wafers used to produce our memory IC products, discontinued the foundry process used to produce such wafers. As a result, in May 2023, we initiated an end-of-life, or EOL, of our memory IC products, and fulfilled all outstanding EOL orders of our memory IC products in March 2025. Subsequent to March 2025, we received two additional purchase orders for our remaining inventory which were fulfilled in the third and fourth quarters of 2025 for total revenues to us of approximately $0.5 million. We may receive additional purchase orders for our remaining inventory, but we do not expect to generate any significant revenue from shipments of our remaining memory IC products after the quarter ended December 31, 2025.

Our ability to compete in the future depends on successfully improving our technology to meet the increasing demand for higher performance and lower cost solutions. Development of new IC products requires specialized chip design and product engineers, expensive computer-aided design software licenses, and significant fabrication and testing costs, including mask costs.

We have over 15 years of technical know-how in the design and manufacturing of mmWave technology. The most important aspect of this knowledge is knowing how mmWave circuits will perform in a real-world environment. Traditionally, semiconductor design utilizes sophisticated computer-aided design software to simulate the performance of a device that is manufactured at a specific semiconductor manufacturing plant. However, mmWave is extremely difficult to model precisely. Therefore, the only path to understand how well a device will perform is to produce the device and test it in a real-world application. Over the last decade, many companies have attempted to develop mmWave semiconductor devices, however, given that the devices had inconsistent or weak performance, a number of the companies were unsuccessful and abandoned their design and product development efforts. As an example of our leadership and expertise in the development of mmWave technology, we were an active participant in the development of the IEEE 802.11ay wireless specification and, to date, have been granted nine essential claims patents with respect to this standard.

At a system level, there are additional technical challenges presented by mmWave technology that we have overcome and form a key part of our internal know-how. For example, a key technology of mmWave is the concept of beamforming and beam steering using a phased-array antenna. This technology is utilized to concentrate the RF energy into a narrow beam to improve the range and coverage of mmWave devices. We have developed effective beamforming and beam steering technology for phased-array circuits and antennas. While there are many academic examples of successful phased-array implementations, there is a vast barrier between a “laboratory” version of phased-array technology and a version that is deployed for commercial use. One such aspect is the implementation of the beamforming procedure, which seeks to maximize throughput and do so while not impacting latency. While the details of achieving this are complex, it is important-intellectual property that we have gained through real-world experience.

mmWave is not without challenges, as mmWave signals do not typically travel as far as traditional wireless signals and are more attenuated by solid objects. Mitigation strategies must be deployed, particularly with regard to the management of signal propagation. Whereas traditional wireless devices utilize a broad, omni-antenna pattern, mmWave systems rely on phased-array technology, which focusses the radio signal into a narrow beam to improve propagation characteristics. We consider ourselves to be a global leader in implementing these sophisticated radio systems and one of the few providers in the market successfully shipping phased-array devices in mass production.

While we have developed products for the 60 GHz and 5G mmWave markets, we believe there are other market opportunities that could utilize mmWave technology. For example, at the IEEE there is a pending proposal to utilize mmWave technology in future versions of an IEEE standard. We believe this proposal is primarily driven by the anticipated use of mmWave to support VR applications, which require very high data rates, and to reduce congestion in multi-dwelling units. In the mobile carrier market, there is some early research in the use of terahertz technology to make even more spectrum available for network capacity. While the proposed frequencies are higher than mmWave (above 100 GHz), we believe that many of our technological developments, particularly our beamforming and beamsteering concepts, can be applied to terahertz technology.

With regard to our memory products, we have ceased and do not intend to expend any development efforts or funds to develop new memory products. Our memory IC products will not provide us with meaningful revenue and gross margin contributions after December 31, 2025, as we completed the EOL of these products during 2025. We intend to continue to devote substantially all of our research and development efforts toward further expanding our mmWave technology portfolio and expanding our product offerings.

In addition to our direct sales personnel, we sell through sales representatives and distributors in the United States, Africa, Asia and Europe. Our distributors have a global presence with offices and technical selling and applications engineering capabilities, which we believe will enable us to reach new potential customers for our products.

We also have applications engineers who support our customer engagements and engage with the customers’ system architects and designers to propose and implement our products and solutions to address system design challenges and improve performance.

In the markets we serve, the time from a design win to production volume shipments of our IC products can range from 12 to 36 months. We believe that our customer systems can have a product life from a few years to up to 10 years once products like ours have been designed into the system. Historically, our revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue.

In the FWA market, our primary customer base is OEMs, but we also have multiple WISP customers primarily located in Africa. Our OEM customers in the fixed wireless space include Ubiquiti, WeLink, which prior to 2024 operated as both an OEM and a WISP, and Tachyon Networks, or Tachyon. Ubiquiti, an OEM in the unlicensed fixed wireless space, relies on us as its sole source mmWave IC supplier for its Wave products. Historically, WeLink relied on us as its sole source supplier for WeLink-designed equipment used to deliver WISP residential service since 2022; however, in 2024, WeLink’s hardware business was launched as a separate entity, Ketsen Networks, or Ketsen. WeLink currently deploys 60 GHz technology in multiple U.S. cities, including Las Vegas, Dallas and Los Angeles. We expect to continue to supply our antenna modules to both WeLink and Ketsen. Tachyon utilizes our mmWave antenna modules in its TNA-30X family of PtP and PtMP solutions for 60 GHz unlicensed FWA networks. In addition to OEMs, we have partnered with several WISPs in Africa that have deployed our 60 GHz technology. We continue to focus on securing new OEM and WISP customers.

During the year ended December 31, 2025, five customers accounted for 10% or more of our net revenues, including UI Limited at 29% and F5/Flextronics, Tachyon and Alltek at 13% each and Ikeja at 12%. During the year ended December 31, 2024, two customers accounted for 10% or more of our net revenues, including Nokia Corporation at 25% and F5/Flextronics at 61%.

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of December 31, 2025, we held 72 United States patents and 16 foreign patents on various aspects of our mmWave, antenna, memory and other technology, with expiration dates ranging from 2026 to 2041. We also held 8 pending patent applications in the United States and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

We were also an active participant in the development of the IEEE 802.11ay wireless specification and, to date, have been granted nine essential claims patents with respect to this standard. Essential claims patents are of particular value as a specification cannot be implemented without obtaining a license to the patents from us.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our IC customers, licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, “Risk Factors.”

mmWave

mmWave circuit and system design is a highly specialized engineering skill, as mmWave is a challenging technology to ship in mass production. At frequencies above 24 GHz, circuits are extremely vulnerable to small variances in the semiconductor manufacturing process. Designing circuits that minimize susceptibility to these variances takes years of development, and we believe we are one of the few companies in the world that is skilled in mmWave design. Further, we have shipped mmWave devices in volume, and ensuring all devices sold adhere to strict performance standards is a core competency we have developed. In addition, we have developed our own mmWave phased-array antenna technology, which allows us to be highly competitive in terms of overall system cost. Our customers do not need to engage with third-party antenna suppliers, thus eliminating the additional cost for a third-party antenna.

Unlicensed IEEE 802.11ad/ay Market:

Historically, our primary competitor in the IEEE802.11ad/ay market has been Qualcomm. The primary benefit that we provide to the market is the support of the higher frequency bands from 66 GHz to 71 GHz. The advantage at these frequencies is that oxygen attenuation is significantly reduced, and signals can travel much further.

We also have key points of differentiation compared to Qualcomm for wireless video devices. We are well positioned in this market, as we have USB 3.0 built into our devices, so our products generally support USB architectures. A prime example is the replacement of the USB cable with a wireless version using our technology. There are many applications where this can be of use, including USB web cams, wireless displays, and AR/VR headsets. We have invested significant software resources into providing the market with wireless USB solutions, and we believe there is no other mmWave vendor in the world that can offer multi-gigabit solutions as a replacement for wired USB.

Licensed 5G Market:

With 5G, our efforts are focused on the mmWave RF front-end phased-array component of the system. The 5G product instantiation is an RF module utilizing our proprietary intellectual property. Key elements of our mmWave intellectual property include:

● RF circuits;

● phased-array antenna; and

● in-system circuit calibration, beam forming, and real-time system monitoring.

From a competitive perspective, we believe we are currently the only pure-play, 5G vendor to offer a dual-band (28/39 GHz) RF solution for the FWA market. Qualcomm does offer a 5G RF solution for the FWA market, however its solution is based on aggregating its mobile RF solution, which we believe requires several compromises in terms of cost, performance, and power consumption. With an initial focus on FWA, we can derive advantages by optimizing our silicon for that specific market. Furthermore, we have achieved traction in the unlicensed, 60 GHz, FWA market, and we believe we will be able to transfer all of our knowledge gained from the 60 GHz market to the 5G market. However, this market opportunity is more competitive, and potential competitors, in addition to Qualcomm, include MediaTek Inc. and Samsung Electronics Co., Ltd.

We depend on third-party vendors to manufacture, package, assemble and test our IC and module products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility. By outsourcing manufacturing, we can avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

We perform an ongoing review of our product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meets design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers.

As of December 31, 2025, we had 42 employees, including 9 located in the United States and 33 located in Canada. Our headcount comprised 31 in research and development and manufacturing-related operations and 11 in sales, marketing and general and administrative functions. We believe our current headcount is adequate to conduct our business.

We were founded in 1991 and reincorporated in Delaware in 2000. Our website address is www.perasoinc.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Exchange Act, as soon as reasonably practicable after they are filed with, or furnished to, the SEC. You can also read any materials submitted electronically by us to the SEC on its website (www.sec.gov), which contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Overview

We are a fabless semiconductor company focused on the development and sale of: i) millimeter wavelength wireless technology, or mmWave, semiconductor devices and antenna modules based on our proprietary semiconductor devices and ii) performance of non-recurring engineering, or NRE, services and licensing of intellectual property, or IP. Our primary focus is the development of mmWave technology for wireless communications. mmWave is generally described as the frequency band from 24 Gigahertz, or GHz, to 300 GHz. Our mmWave products, which primarily operate in the spectrum from 24 GHz to 71 GHz, enable a range of applications including: multi-gigabit point-to-point, or PtP, wireless links with a range of up to 25 kilometers and operating in the 60 GHz frequency band; multi-gigabit point-to-multi-point, or PtMP, links in the 60 GHz frequency band used to provide fixed wireless access, or FWA, services; FWA in the 5G operating bands from 24 GHz to 43 GHz to provide multi-gigabit capability and low latency connections; military communications; and consumer applications, such as high performance wireless video streaming and untethered augmented reality and virtual reality. We also have a line of memory-denominated integrated circuits, or ICs, for high-speed cloud networking, communications, security appliance, video, monitor and test, data center and computing markets that deliver time-to-market, performance, power, area and economic benefits for system original equipment manufacturers, or OEMs. As discussed below, we initiated an end-of-life of these products in 2023 and expect to complete final shipments in March 2025.

Business Combination

We were formerly known as MoSys, Inc., or MoSys. On September 14, 2021, we and our subsidiaries, 2864552 Ontario Inc. and 2864555 Ontario Inc., entered into an Arrangement Agreement, or the Arrangement Agreement, with Peraso Technologies Inc., or Peraso Tech, a privately-held corporation existing under the laws of the province of Ontario, to acquire all of the issued and outstanding common shares of Peraso Tech, or the Peraso Shares, including those Peraso Shares to be issued in connection with the conversion or exchange of secured convertible debentures and common share purchase warrants of Peraso Tech, as applicable, by way of a statutory plan of arrangement, or the Arrangement, under the Business Corporations Act (Ontario). On December 17, 2021, following the satisfaction of the closing conditions set forth in the Arrangement Agreement, the Arrangement was completed, and we changed our name from MoSys to “Peraso Inc.” and began trading on The Nasdaq Stock Market, or the Nasdaq, under the symbol “PRSO.” Certain previous shareholders of Peraso Tech elected to convert their Peraso Tech common stock into exchangeable shares in 2864555 Ontario Inc., one of our wholly-owned subsidiaries. These exchangeable shares, which can be converted into our common stock at the option of the holder, are similar in substance to our common stock.

Industry Trends and Market Opportunities

mmWave

Historically, virtually all wireless communications have utilized the frequency spectrum below 6 GHz. Primary examples include cell phone communications, WiFi, Bluetooth, Internet of Things, and more recently, broadband internet access or FWA. In parallel, a broad array of applications continues to push the boundaries of available wireless network capacity. These include video streaming services, such as those offered by Netflix, Apple and Amazon, user-generated video content, such as TikTok and Instagram Reels, and broadly, personal video content generated by personal mobile devices.

While the sub-6 GHz band has traditionally been sufficient for these services, with growing demand, the mmWave spectrum is an additional source of wireless capacity. Wireless spectrum is an extremely valuable commodity and is highly regulated by federal governments around the world. Spectrum is broadly segmented into either licensed frequencies or unlicensed frequencies, although most frequencies are licensed. The mmWave frequencies between 24 GHz and 100 GHz include both licensed and unlicensed spectrum. In the case of mmWave, the 3rd Generation Partnership Project, or 3GPP, has included the spectrum from 24 GHz to 43 GHz in its 5G specification. This is licensed spectrum in most jurisdictions around the world, and carriers must license this spectrum if they choose to utilize the mmWave frequency bands within that spectrum. Alternatively, the spectrum from 57 GHz to 71 GHz is generally unlicensed around the world, and, therefore, a license is not required to operate in this spectrum. To that end, the Institute of Electrical and Electronics Engineers, or IEEE, has established two standards which utilize this unlicensed mmWave spectrum, IEEE 802.11ad and IEEE 802.11ay. We have developed silicon products that comply with both the licensed and unlicensed standards.

In an August 2024 report titled, Millimeter Wave Technology, Allied Market Research valued the global mmWave technology market at $3.4 billion, and forecasted it to grow at a 20% compound annual growth rate from 2024 to 2032.

IEEE 802.11ad/ay: License-Free mmWave Market

A primary opportunity for our mmWave products in unlicensed-band applications is the FWA market. In this market segment, wireless Internet service providers, or WISPs, provide their customers with a fixed wireless link to a base station or small cell, thus providing the customer with high-speed access to the Internet. mmWave can provide both upload and download speeds of over 1 Gbps. In addition, we believe mmWave is generally a much less expensive alternative to installing underground fiber optic cable and provides FWA carriers with competitive and cost advantages compared to other access technologies, such as cable broadband. From an equipment perspective, the FWA worldwide market has historically been serviced by OEMs, such as Ubiquiti Inc., or Ubiquiti, Cambium Networks, Ltd. and SIA MikroTik. Generally, WISPs address segments of the broadband market either not served or underserved by the traditional carriers, such as rural markets.

The FWA market has been helped in recent years with the advent of government incentives aimed at closing the so-called ‘digital divide’ between urban and rural broadband access. In 2023, the U.S. government established the Broadband Equity, Access, and Deployment, or BEAD, program, which allocated $42.45 billion to expand high-speed Internet access by funding planning, infrastructure deployment and adoption programs in all 50 states. The National Telecommunications and Information Administration, or NTIA, is the agency responsible for administering the BEAD program. When initially introduced, the NTIA had originally provided guidance that BEAD funding would be prioritized for primarily fiber deployments, and that alternative technologies such as unlicensed fixed wireless were not eligible for BEAD program funding. On February 4, 2025, Arielle Roth was nominated to take over leadership of the NTIA. Ms. Roth, speaking at a Federalist Society event in June, 2024, stated that the NTIA has “imposed extreme tech bias in favor of fiber.” On March 4, 2025, the Wall Street Journal reported that the U.S. Commerce Secretary, Howard Lutnick, has told staff he plans to make the BEAD program technology neutral. A shift to a technology-neutral approach would include all forms of FWA, including our 60GHz mmWave wireless technology.

A related opportunity for us in the license-free FWA space is dense urban markets, many of which have a high saturation of informal settlements. In a December 2023 report, the International Telecommunications Union, or ITU, reported that an estimated 2.6 billion people, or one-third of the global population, does not have Internet access. As of August 2023, the World Economic Forum estimated there were over 1.1 billion people living in informal settlements around the world. Traditional last mile technology, such as WiFi, is not able to handle the congestion generated by the dense concentration of users in such communities. This is because WiFi radio signals spread out in all directions, much like a light bulb. Due to the very high population density in informal settlements, numerous WiFi transmitters are required, and as such, tend to cancel each other out with overlapping signals. Because our mmWave technology utilizes beamforming, the signals are more like beams from a car headlight, very narrow and controlled. Therefore, in a dense environment, mmWave is much better at handling high congestion, as the radio signals generally do not overlap. Another advantage our mmWave technology provides in the dense urban environment is reduced power consumption. The power grid in an informal settlement can often be unreliable. Our technology can operate under 12 watts, which enables communications networks to continue to operate on a backup battery power supply for several hours.

An additional market for our 60GHz mmWave products is military applications. Specifically, as a result of our radio frequency, or RF, beamforming and beamsteering capabilities, militaries and their defense contractors are evaluating the use of mmWave for stealth tactical communications. Unlike traditional wireless technology that radiates equally in all directions (omni), mmWave technology utilizes phased-array RF beams to focus the RF energy into a specific intensity and direction. The military views mmWave as an inherently stealthy protocol – Low Probability of Interception (LPI)/Low Probability of Detection (LPD)/Anti-Jamming (AJ). As the 60GHz spectrum band is generally unlicensed around the world, these communications will not interfere with locally licensed spectrum, providing additional benefit. Also, as our devices operate at under 12 watts, a light battery can be used for simple deployment in field deployments and combat settings. Further, as our mmWave technology can support gigabit speeds, military personnel are able to transmit and receive information in a timely manner. We are engaged with multiple defense contractors, and in 2023, we were awarded a proof-of-concept license and technology development contract. We received an additional engagement for our mmWave products in 2024, and we expect to commence initial shipments for this engagement by mid 2025.

Our 60 GHz products can also be applied to consumer applications, as we believe our technology can provide key advantages to this market. For example, we are targeting the high-performance, video-streaming market, specifically the virtual reality, or VR, market. Uses of VR are envisioned in a broad variety of markets, including gaming, real estate, healthcare, and transportation. We believe that our mmWave technology has certain characteristics that are ideal for VR applications. First, mmWave’s high data rate of 3 Gbps supports high-resolution displays. Second, our proprietary beamforming and beamtracking techniques keep latency to under 5 milliseconds, or ms, so the user does not experience lags. Third, mmWave technology is less susceptible to interference and, as mentioned above in the context of dense urban environments, can operate in highly congested environments, which limits interruptions in the VR user’s experience.

Other market opportunities for 60 GHz mmWave technology include transportation safety, factory automation, and railway communications.

3GPP: Licensed mmWave Market

The frequency band from 24 GHz to 43 GHz has been designated as the mmWave band in 5G communications. In the United States, this band is generally licensed to carriers by the FCC for expensive license fees that can reach billions of dollars. Carriers license this spectrum to ensure there is no interference from other carriers using the same frequencies. We believe that the primary benefit of mmWave to carriers is the availability of additional spectrum within the licensed band, to provide additional capacity to handle the growth of mobile users.

Our initial target for licensed-band applications is the FWA segment, as carriers can utilize the additional network capacity offered by mmWave to provide FWA services. According to the Ericsson Mobility Report, as of November 2023, approximately 80% of mobile service providers have an FWA offering and 121 service providers offer FWA services over 5G, representing 50% of all FWA service providers. According to Mobile Experts Inc.’s report, 5G Millimeter Wave 2023, mobile operators that have deployed 5G mmWave include Verizon, T-Mobile, AT&T, NTT DoCoMo, KDDI, Softbank and Rakuten Mobile. We believe major Chinese mobile carriers have commenced formal collaborations to advance mmWave solutions in the Chinese telecom market. Regarding U.S. carriers, FWA has become a bright spot for their 5G roll out. While U.S. carriers currently use the sub 6 GHz frequency band, eventually, as the network gets saturated, we believe the carriers will commence a broad roll out of mmWave technology. In terms of FWA market potential in the U.S., according to Fierce Wireless, T-Mobile is available to over 50 million homes, and Verizon is available to over 40 million homes. In addition to being used to provide FWA services, our mmWave antenna modules can be utilized in consumer-premises equipment or CPE, including hotspots, laptops and tablets. In its report, 5G Millimeter Wave 2023, Mobile Experts Inc. forecasts a total volume of approximately 2 million mmWave-enabled CPE units by 2026.

5G mmWave has support from major industry players, such as Apple, which has incorporated mmWave wireless into substantially all versions of the iPhone for sale in the U.S. market. The basic premise is the ever-increasing demand for bandwidth. The initial use case for cellular service providers is to provide their customer base (primarily smart-phone customers) with continuity of network access in highly congested environments, such as sporting events, public beaches, music festivals or generally any large gathering where thousands of users are attempting to access the network simultaneously. We believe that mmWave will gain universal acceptance, as users will demand full continuity in terms of network access, and we are well positioned to address the mobile opportunity for mmWave, which is expected to present an order of magnitude increase in the total available market.

Our Products

Our primary focus is the development, marketing and sale of our mmWave products.

mmWave ICs

Currently, there are two industry standards that incorporate mmWave technology for wireless communications: (i) license-free: IEEE 802.11ad/ay and (ii) licensed: 3GPP Release 15-17 (commonly referred to as 5G). We have developed and continue to develop products that conform to these standards. To date, we have not sold any 5G products, as our primary business focus remains license-free markets.

Our first mmWave IC product line operates in the license-free 60 GHz band and conforms to the IEEE 802.11ad standard. This product line includes a baseband IC, several variations of mmWave radio frequency, or RF, ICs, and associated antenna technology.

Our 60 GHz IEEE802.11ad products have two very important advantages over traditional 2.4 GHz / 5 GHz Wi-Fi products: very high data rates (up to 3.0 Gbps) and low latency, i.e., less than 5 ms. The first application that had traction was outdoor broadband, including applications such as PtP backhaul links or FWA using PtMP links. As the spectrum is unlicensed (free), WISPs can provide services without having to procure expensive wireless spectrum licenses. We believe that our mmWave technology can be deployed quickly and cost effectively in rural and suburban environments, including in remote and low-income regions where residents often have poor Internet quality. While carriers can provide fiber access, the cost of fiber deployment can be prohibitive and trenching for fiber is time consuming and can limit the rate at which new subscribers are added. Our mmWave products enable WISPs to deploy broadband service using low-cost terminals and infrastructure, while avoiding the costs of deploying cable or fiber.

We are a leading supplier of semiconductors in the mmWave PtP and PtMP markets. We are currently shipping to leading equipment suppliers in this space, as well as directly to service providers that are building their own equipment. We believe we bring certain advantages to the market, including our products supporting the spectrum from 66 GHz to 71 GHz, which is often referred to as channels 5 and 6 in the 802.11ad/ay specifications. The key advantage in supporting these channels is that the signals are able to propagate much further than channels 1 through 4; this is a result of significantly lower oxygen absorption at frequencies above 66 GHz. To date, our FWA customers have achieved links in the range of 25 kilometers, which we believe is industry-leading.

In the indoor area, the 802.11ad technology is ideal for high-speed, low-latency video applications, and our products can support 3Gbps links with under 5 ms of latency. Representative applications include:

● AR/VR links between the headset and the video console;

● USB video cameras for corporate video conferencing;

● wireless security cameras; and

● smart factory safety and surveillance.

Our mmWave ICs have been in volume production since 2018. A core competency of the Company is phased-array technology, or beamforming, in which an array of antenna elements work in unison to create a focused RF beam. Through adjustment of the relative phase of the antenna signals, the beams can be directed to support robust wireless connection. We are a leader in the production of mmWave devices and have pioneered a high-volume mmWave production test methodology using standard low-cost production test equipment. It has taken us several years to refine performance of this production test methodology, and we believe this places us in a leadership position in addressing the operational challenges of delivering mmWave products into high-volume markets.

Our second product line addresses the 5G mmWave opportunity. In its 4G-5G FWA Survey 2024 issued in August 2024, the Global Mobile Supplier Association reported that 5G mmWave FWA was ramping and that shipments of 5G devices with mmWave capability are expected to grow 22% in 2024, while still representing less than 10% of all 5G device shipments. Given our extensive experience in the development of mmWave technology, 5G mmWave is a logical adjacent and larger market. We have sampled a highly integrated 5G mmWave beamformer IC, which operates in the 24 GHz to 43 GHz frequency range. The device supports dual-stream multiple input, multiple output, or MIMO, with two 16-channel beamforming arrays. In June 2023, we announced a collaboration with pSemi, a Murata company, for the development of a 5G customer premise receiver utilizing our beamformer IC and pSemi’s up-down converter IC. The goals of the collaboration are to reduce the number of components and cost of each RF module to promote faster time to market for more rapid deployment by prospective customers.

mmWave Antenna Modules

We produce and sell complete mmWave antenna modules for license-free 60 GHz applications. The primary advantage provided by our antenna modules is that our proprietary mmWave ICs and the antenna are integrated into a single device. A differentiating characteristic of mmWave technology is that the RF amplifiers must be as close as possible to the antenna to minimize loss. With our module, we can guarantee the performance of the amplifier/antenna interface and simplify customers’ RF engineering, facilitating more opportunities for customer prospects that have not provided RF-type systems, as well as shortening the time to market for new products. It is possible for third parties to provide competitive module products, but, because we utilize our mmWave ICs and incorporate our proprietary mmWave antenna IP, we can provide a highly-competitive solution based on our internally-owned and developed module components.

Our PERSPECTUS family of mmWave antenna modules enable WISPs to offer high-capacity FWA networks in the unlicensed 60-GHz spectrum. The PERSPECTUS product family includes our integrated 60 GHz mmWave antenna modules and enhanced software for PtMP FWA applications. Our PERSPECTUS products allow rapid development of low-cost network equipment utilizing over 14 GHz of spectrum to provide multi-gigabit access services. Leveraging our integrated phased-array antennas and operating in the upper channels of the band, link ranges from 1.5 kilometers up to extended ranges of 30 kilometers can be achieved using a parabolic reflector.

Additionally, we have established an innovative user arbitration protocol called DUNE that is specifically designed to optimize network performance in dense urban environments using our PERSPECTUS antenna modules. DUNE is a result of our decade-long experience in mmWave technology and in-house development of the intellectual property incorporated in media access control, which controls the hardware, the physical layer, which controls the physical connection and software drivers, as well as novel antenna designs and beamforming algorithms. DUNE takes a multi-level approach to reducing contention and interference by incorporating both physical, e.g. antenna and beamforming, and protocol-level innovations.

Memory

Our memory products comprise our Bandwidth Engine ICs, which are memory-dominated ICs that were designed to be i) high-performance companion ICs to packet processors and ii) targeted for high-performance applications where throughput is critical. These products integrate our proprietary, 1T-SRAM high-density embedded memory and a highly-efficient serial interface protocol resulting in a monolithic memory IC solution optimized for memory bandwidth and transaction access performance. Taiwan Semiconductor Manufacturing Corporation, or TSMC, is the sole foundry that manufactures the wafers used to produce our memory IC products. TSMC informed us that it would be discontinuing the foundry process used to produce wafers, in turn, necessary to manufacture our memory ICs. As a result, in May 2023, we initiated an end-of-life, or EOL, of our memory IC products, and we commenced initial EOL shipments during the quarter ended September 30, 2023. As of December 31, 2024, we had remaining EOL purchase orders totaling approximately $2.3 million, and we expect to ship all of these orders by March 2025. We do not expect any further shipments or to generate any revenue from shipments of our memory IC products after March 2025.

Research and Development

Our ability to compete in the future depends on successfully improving our technology to meet the increasing demand for higher performance and lower cost solutions. Development of new IC products requires specialized chip design and product engineers, expensive computer-aided design software licenses, and significant fabrication and testing costs, including mask costs.

We have over 15 years of technical know-how in the design and manufacturing of mmWave technology. The most important aspect of this knowledge is knowing how mmWave circuits will perform in a real-world environment. Traditionally, semiconductor design utilizes sophisticated computer-aided design software to simulate the performance of a device that is manufactured at a specific semiconductor manufacturing plant. However, mmWave is extremely difficult to model precisely. Therefore, the only path to understand how well a device will perform is to produce the device and test it in a real-world application. Over the last decade, many companies have attempted to develop mmWave semiconductor devices, however, given that the devices had inconsistent or weak performance, a number of the companies were unsuccessful and abandoned their design and product development efforts. As an example of our leadership and expertise in the development of mmWave technology, we were an active participant in the development of the IEEE 802.11ay wireless specification and, to date, have been granted nine essential claims patents with respect to this standard.

At a system level, there are additional technical challenges presented by mmWave technology that we have overcome and form a key part of our internal know-how. For example, a key technology of mmWave is the concept of beamforming and beam steering using a phased-array antenna. This technology is utilized to concentrate the RF energy into a narrow beam to improve the range and coverage of mmWave devices. We have developed effective beamforming and beam steering technology for phased-array circuits and antennas. While there are many academic examples of successful phased-array implementations, there is a vast barrier between a “laboratory” version of phased-array technology and a version that is deployed for commercial use. One such aspect is the implementation of the beamforming procedure, which seeks to maximize throughput and do so while not impacting latency. While the details of achieving this are complex, it is important-intellectual property that we have gained through real-world experience.

mmWave is not without challenges, as mmWave signals do not typically travel as far as traditional wireless signals and are more attenuated by solid objects. Mitigation strategies must be deployed, particularly with regard to the management of signal propagation. Whereas traditional wireless devices utilize a broad, omni-antenna pattern, mmWave systems rely on phased-array technology, which focusses the radio signal into a narrow beam to improve propagation characteristics. We consider ourselves to be a global leader in implementing these sophisticated radio systems and one of the few providers in the market successfully shipping phased-array devices in mass production.

While we have developed products for the 60 GHz and 5G mmWave markets, we believe there are other market opportunities that could utilize mmWave technology. For example, in the WiFi Alliance there is a pending proposal to utilize mmWave technology in WiFi 8, which is the next generation of WiFi technology. We believe this proposal is primarily driven by the anticipated use of mmWave to support VR applications, which require very high data rates, and to reduce congestion in multi-dwelling units. In the mobile carrier market, there is some early research in the use of terahertz technology to make even more spectrum available for network capacity. While the proposed frequencies are higher than mmWave (above 100 GHz), we believe that many of our technological developments, particularly our beamforming and beamsteering concepts, can be applied to terahertz technology.

With regard to our memory products, we have ceased and do not intend to expend any development efforts or funds to develop new memory products. We believe our Bandwidth Engine IC products will provide us with meaningful revenue and gross margin contributions through March 31, 2025, as we complete the EOL of these products. We intend to continue to devote substantially all of our research and development efforts toward further expanding our mmWave technology portfolio and expanding our product offerings.

Sales and Marketing

In addition to our direct sales personnel, we sell through sales representatives and distributors in the United States, Asia and Europe. Our distributors have a global presence with offices and technical selling and applications engineering capabilities, which we believe will enable us to reach new potential customers for our products.

We also have applications engineers who support our customer engagements and engage with the customers’ system architects and designers to propose and implement our products and solutions to address system design challenges and improve performance.

In the markets we serve, the time from a design win to production volume shipments of our IC products can range from 12 to 36 months. We believe that our customer systems can have a product life from a few years to up to 10 years once products like ours have been designed into the system. Historically, our revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue.

In the FWA market, our primary customer base is OEMs, but we also have multiple WISP customers in the U.S. and Canada. Our OEM customers in the fixed wireless space include Ubiquiti, WeLink, which prior to 2024 operated as both an OEM and a WISP, Tachyon Networks, or Tachyon, and China Unicom. Ubiquiti, an OEM in the unlicensed fixed wireless space, relies on us as its sole source mmWave IC supplier for its Wave products, which Ubiquiti introduced in 2022. Ubiquiti introduced three new Wave models in 2023. Historically, WeLink relied on us as its sole source supplier for WeLink-designed equipment used to deliver WISP residential service since 2022; however, in 2024, WeLink’s hardware business was launched as a separate entity, Ketsen Networks, or Ketsen. WeLink currently deploys 60 GHz technology in multiple U.S. cities, including Las Vegas, Dallas and Los Angeles. We expect to continue to supply our antenna modules to both WeLink and Ketsen. Tachyon utilizes our mmWave antenna modules in its TNA-30X family of PtP and PtMP solutions for 60 GHz unlicensed FWA networks. Peraso and Tachyon jointly announced production readiness of the TNA-30X product family in June 2023. Finally, China Unicom is a Chinese mobile carrier that uses our 60 GHz technology for 5G PtP backhaul. In addition to OEMs, we have partnered with several WISPs in the U.S. and Canada that have deployed our 60 GHz technology, including WeLink. We continue to focus on securing new OEM and WISP customers.

During the year ended December 31, 2024, two customers accounted for 10% or more of our net revenues, including Nokia Corporation at 25% and F5/Flextronics at 61%. During the year ended December 31, 2023, three customers accounted for 10% or more of our net revenues, including Nokia Corporation at 35%, F5/Flextronics at 22% and Alltek Technology Corp at 18%.

Intellectual Property

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of March 1, 2025, we held 87 United States patents and 27 foreign patents on various aspects of our mmWave, antenna, memory and other technology, with expiration dates ranging from 2025 to 2041. We also held 11 pending patent applications in the United States and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

We were also an active participant in the development of the IEEE 802.11ay wireless specification and, to date, have been granted nine essential claims patents with respect to this standard. Essential claims patents are of particular value as a specification cannot be implemented without obtaining a license to the patents from us.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our IC customers, licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, “Risk Factors.”

Competition

mmWave

mmWave circuit and system design is a highly specialized engineering skill, as mmWave is a challenging technology to ship in mass production. At frequencies above 24 GHz, circuits are extremely vulnerable to small variances in the semiconductor manufacturing process. Designing circuits that minimize susceptibility to these variances takes years of development, and we believe we are one of the few companies in the world that is skilled in mmWave design. Further, we have shipped mmWave devices in volume, and ensuring all devices sold adhere to strict performance standards is a core competency we have developed. In addition, we have developed our own mmWave phased-array antenna technology, which allows us to be highly competitive in terms of overall system cost. Our customers do not need to engage with third-party antenna suppliers, thus eliminating the additional cost for a third-party antenna.

Unlicensed IEEE 802.11ad/ay Market:

Historically, our primary competitor in the IEEE802.11ad/ay market has been Qualcomm. The primary benefit that we provide to the market is the support of the higher frequency bands from 66 GHz to 71 GHz. The advantage at these frequencies is that oxygen attenuation is significantly reduced, and signals can travel much further.

We also have key points of differentiation compared to Qualcomm for wireless video devices. We are well positioned in this market, as we have USB 3.0 built into our devices, so our products generally support USB architectures. A prime example is the replacement of the USB cable with a wireless version using our technology. There are many applications where this can be of use, including USB web cams, wireless displays, and AR/VR headsets. We have invested significant software resources into providing the market with wireless USB solutions, and we believe there is no other mmWave vendor in the world that can offer multi-gigabit solutions as a replacement for wired USB.

Licensed 5G Market:

With 5G, our efforts are focused on the mmWave RF front-end phased-array component of the system. The 5G product instantiation is an RF module utilizing our proprietary intellectual property. Key elements of our mmWave intellectual property include:

● RF circuits;

● phased-array antenna; and

● in-system circuit calibration, beam forming, and real-time system monitoring.

From a competitive perspective, we believe we are currently the only pure-play, 5G vendor to offer a dual-band (28/39 GHz) RF solution for the FWA market. Qualcomm does offer a 5G RF solution for the FWA market, however its solution is based on aggregating its mobile RF solution, which we believe requires several compromises in terms of cost, performance, and power consumption. With an initial focus on FWA, we can derive advantages by optimizing our silicon for that specific market. Furthermore, we have achieved traction in the unlicensed, 60 GHz, FWA market, and we believe we will be able to transfer all of our knowledge gained from the 60 GHz market to the 5G market. However, this market opportunity is more competitive, and potential competitors, in addition to Qualcomm, include MediaTek Inc. and Samsung Electronics Co., Ltd.

Manufacturing

We depend on third-party vendors to manufacture, package, assemble and test our IC and module products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility. By outsourcing manufacturing, we can avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

We perform an ongoing review of our product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meets design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers.

Employees

As of December 31, 2024, we had 42 employees, including 12 located in the United States and 30 located in Canada. Our headcount comprised 29 in research and development and manufacturing-related operations and 13 in sales, marketing and general and administrative functions. We believe our current headcount is adequate to conduct our business.

Available Information

We were founded in 1991 and reincorporated in Delaware in 2000. Our website address is www.perasoinc.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Exchange Act, as soon as reasonably practicable after they are filed with, or furnished to, the SEC. You can also read any materials submitted electronically by us to the SEC on its website (www.sec.gov), which contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

We are a fabless semiconductor company focused on the development and sale of: i) millimeter wavelength wireless technology, or mmWave, semiconductor devices and antenna modules based on our proprietary semiconductor devices and ii) performance of non-recurring engineering, or NRE, services and licensing of intellectual property, or IP. Our primary focus is the development of mmWave, which is generally described as the frequency band from 24 Gigahertz, or GHz, to 300 GHz. Our mmWave products enable a range of applications including: multi-gigabit point-to-point, or PtP, wireless links with a range of up to 25 kilometers and operating in the 60 GHz frequency band; multi-gigabit point-to-multi-point, or PtMP, links in the 60 GHz frequency band used to provide fixed wireless access, or FWA, services; FWA in the 5G operating bands from 24 GHz to 43 GHz to provide multi-gigabit capability and low latency connections; military communications; and consumer applications, such as high performance wireless video streaming and untethered augmented reality and virtual reality. We also have a line of memory-denominated integrated circuits, or ICs, for high-speed cloud networking, communications, security appliance, video, monitor and test, data center and computing markets that deliver time-to-market, performance, power, area and economic benefits for system original equipment manufacturers, or OEMs. As discussed below, we initiated an end-of-life of these products in 2023.

We were formerly known as MoSys, Inc., or MoSys. On September 14, 2021, we and our subsidiaries, 2864552 Ontario Inc. and 2864555 Ontario Inc., entered into an Arrangement Agreement, or the Arrangement Agreement, with Peraso Technologies Inc., or Peraso Tech, a privately-held corporation existing under the laws of the province of Ontario, to acquire all of the issued and outstanding common shares of Peraso Tech, or the Peraso Shares, including those Peraso Shares to be issued in connection with the conversion or exchange of secured convertible debentures and common share purchase warrants of Peraso Tech, as applicable, by way of a statutory plan of arrangement, or the Arrangement, under the Business Corporations Act (Ontario). On December 17, 2021, following the satisfaction of the closing conditions set forth in the Arrangement Agreement, the Arrangement was completed, and we changed our name from MoSys to “Peraso Inc.” and began trading on The Nasdaq Stock Market, or the Nasdaq, under the symbol “PRSO.” Certain previous shareholders of Peraso Tech elected to convert their Peraso Tech common stock into exchangeable shares in 2864555 Ontario Inc., one of our wholly-owned subsidiaries. These exchangeable shares, which can be converted into our common stock at the option of the holder, are similar in substance to our common stock.

Historically, virtually all wireless communications has utilized the frequency spectrum below 6 GHz. Primary examples include cell phone communications, WiFi, Bluetooth, Internet of Things, or IoT, and more recently, broadband internet access or FWA. In parallel, a broad array of applications continues to push the boundaries of available wireless network capacity. These include video streaming services, such as those offered by Netflix, Apple and Amazon, user-generated video content, such as TikTok and Instagram Reels, and broadly, personal video content generated by personal mobile devices.

While the sub-6 GHz band has traditionally been sufficient for these services, with growing demand, the industry is migrating towards mmWave spectrum as an additional source of wireless capacity. Wireless spectrum is an extremely valuable commodity and is highly regulated by federal governments around the world. Spectrum is broadly segmented into either licensed frequencies or unlicensed frequencies, although most frequencies are licensed. This holds true for mmWave frequencies between 24 GHz and 100 GHz. In the case of mmWave, the 3rd Generation Partnership Project, or 3GPP, has included the spectrum from 24 GHz to 43 GHz in its 5G specification. This is licensed spectrum in most jurisdictions around the world, and carriers must license this spectrum if they choose to utilize the mmWave frequency bands within that spectrum. Alternatively, the spectrum from 57 GHz to 71 GHz is generally unlicensed around the world, and, therefore, a license is not required to operate in this spectrum. To that end, the Institute of Electrical and Electronics Engineers, or IEEE, has established two standards which utilize this unlicensed mmWave spectrum, IEEE 802.11ad and IEEE 802.11ay. Peraso has developed silicon products that comply with both the licensed and unlicensed standards.

IEEE 802.11ad/ay: License-Free mmWave Market

A primary opportunity for our mmWave products in unlicensed-band applications is the FWA market. In this market segment, wireless Internet service providers, or WISPs, provide their customers with a fixed wireless link to a base station or small cell, thus providing the customer with high-speed access to the Internet. mmWave can provide both upload and download speeds of over 1 Gbps. In addition, we believe mmWave can be a less expensive alternative to installing fiber and allows FWA carriers a competitive advantage against other access technologies, such as cable broadband. From an equipment perspective, this worldwide market has historically been serviced by FWA OEMs, such as Ubiquiti Inc., or Ubiquiti, Cambium Networks, Ltd. and SIA MikroTik. WISPs are addressing a segment of the broadband market not served by the traditional carriers, or, in some cases, underserved by the carriers.

The FWA market has been helped in recent years with the advent of government incentives aimed at closing the so-called ‘digital divide’ between urban and rural broadband access. The WISP market is experiencing strong growth. According to The 2021 Fixed-Wireless and Hybrid ISP Industry Report prepared by the Carmel Group, the number of subscribers that WISP providers serve in the United States is expected to grow from 6.9 million at the end of 2020 to 12.7 million by the end of 2025. Additionally, the U.S. government has allocated significant support for the improvement of broadband access to underserved and unserved communities. In 2020, the U.S. Federal Communications Commission, or FCC, established the Rural Digital Opportunity Fund, or RDOF, to award up to $20.4 billion for the development of improved broadband in rural communities. In 2023, the U.S. government established the Broadband Equity, Access, and Deployment, or BEAD, program, which has allocated $42.45 billion to expand high-speed Internet access by funding planning, infrastructure deployment and adoption programs in all 50 states.

A related opportunity for us in the license-free FWA space is dense urban markets, many of which have a high saturation of informal settlements. As of August 2023, the World Economic Forum estimates there are over 1.1 billion people living in informal settlements around the world. Traditional last mile technology, such as WiFi, is not able to handle to the congestion of users in such communities. This is because WiFi radio signals spread out in all directions, much like a bare incandescent light bulb. Due to the very high population density in informal settlements, many WiFi transmitters are required, and as such, tend to cancel each other out with overlapping signals. Because our mmWave technology utilizes beamforming, the signals are more like beams from a car headlight, very narrow and controlled. Therefore, in a dense environment, mmWave is much better at handling high congestion, as the radio signals generally do not overlap. Another advantage our mmWave technology provides in the dense urban environment is reduced power consumption. The power grid in an informal settlement can often be unreliable. Our technology can operate under 12 watts, which enables communications networks to continue to operate on a backup battery power supply for several hours.

An additional market for Peraso 60GHz mmWave products is military applications. Specifically, as a result of our RF beamforming and beamsteering capability, the military is considering the use of mmWave for stealth tactical communications. Unlike traditional wireless technology that radiates equally in all directions (omni), mmWave technology utilizes phased-array RF beams to focus the RF energy into a specific intensity and direction. The military refers to mmWave as an inherently stealthy protocol – Low Probability of Interception (LPI)/Low Probability of Detection (LPD)/Anti-Jamming (AJ). An additional benefit of using the 60GHz spectrum, is since this band is generally unlicensed around the world, these communications will not interfere with locally licensed spectrum. Also, as our devices operate at under 12 watts, a light battery can be used for simple deployment in combat settings. Further, as our mmWave technology can support gigabit speeds, military personnel are able to transmit and receive information in a timely manner. In 2023, we were awarded a proof-of-concept license and technology development contract to enable mmWave-based communications between soldiers and their vehicle.

Our 60 GHz products can also be applied to consumer applications, as we believe our technology can provide key advantages to this market. For example, we are targeting the high-performance, video-streaming market, specifically the virtual reality, or VR, market. In its market report, Virtual Reality Data: Devices, Verticals, and Value Chain – 1Q 2022, ABI Research estimates a market opportunity of over 6 million VR headsets by the end of 2025, which we believe translates into a total available market for us in 2025 of approximately $180 million, assuming an average selling price to us of $30 for an antenna module included in each VR headset. Uses of VR are envisioned in a broad variety of markets, including gaming, real estate, healthcare, and transportation. We believe that our mmWave technology has certain characteristics that are ideal for VR applications. First, mmWave’s high data rate of 3 Gbps supports high-resolution displays. Second, our proprietary beamforming and beamtracking techniques keep latency to under 5 milliseconds, or ms, so the user does not experience lags in the experience. Third, mmWave technology is less susceptible to interference and, as mentioned above in the context of dense urban environments, can operate in highly congested environments, which limits interruptions in the VR user’s experience.

Other market opportunities for 60 GHz mmWave technology include transportation safety, factory automation, and railway communications.

3GPP: Licensed mmWave Market

The frequency band from 24 GHz to 43 GHz has been designated as the mmWave band in 5G communications. In the United States, this band is generally licensed to carriers by the FCC for expensive license fees that can reach billions of dollars. Carriers license this spectrum to ensure there is no interference from other carriers using the same frequencies. We believe that the primary benefit of mmWave to carriers is the availability of additional spectrum within the licensed band, to provide additional capacity to handle the growth of mobile users. In its report, 5G Millimeter Wave 2023, Mobile Experts Inc. predicts that, based on current user growth predictions, U.S. carriers will saturate the capacity of their networks using existing spectrum by 2025, and will need to utilize mmWave to provide additional capacity.

Our initial target for licensed-band applications is the FWA segment, as carriers can utilize the additional network capacity offered by mmWave to provide FWA services. According to the Ericsson Mobility Report, as of November 2023, approximately 80% of mobile service providers have an FWA offering and 121 service providers offer FWA services over 5G, representing 50% of all FWA service providers. According to Mobile Experts Inc.’s report, 5G Millimeter Wave 2023, mobile operators that have deployed 5G mmWave include Verizon, T-Mobile, AT&T, NTT DoCoMo, KDDI, Softbank and Rakuten Mobile. We believe major Chinese mobile carriers have commenced formal collaborations to advance mmWave solutions in the Chinese telecom market. Regarding U.S. carriers, FWA has become a bright spot for their 5G roll out. According to Light Reading, fixed wireless services accounted for over 90% of all net broadband customer additions in the U.S. during 2022. While U.S. carriers currently use the sub 6 GHz frequency band, eventually, as the network gets saturated, we believe the carriers will commence a broad roll out of mmWave technology. In terms of FWA market potential in the U.S., according to Fierce Wireless, T-Mobile is available to over 50 million homes, and Verizon is available to over 40 million homes. In addition to being used to provide FWA services, our mmWave antenna modules can be utilized in consumer-premises equipment or CPE, including hotspots, laptops and tablets. In its report, 5G Millimeter Wave 2023, Mobile Experts Inc. forecasts a total volume of approximately 2 million mmWave-enabled CPE units by 2026.

5G mmWave has support from major industry players, such as Apple, which has incorporated mmWave wireless into substantially all versions of the iPhone for sale in the U.S. market. The basic premise is the ever-increasing demand for bandwidth. The initial use case for cellular service providers is to provide their customer base (primarily smart-phone customers) with continuity of network access in highly congested environments, such as sporting events, public beaches, music festivals or generally any large gathering where thousands of users are attempting to access the network simultaneously. We believe that mmWave will gain universal acceptance, as users will demand full continuity in terms of network access, and we are well positioned to address the mobile opportunity for mmWave, which is expected to present an order of magnitude increase in the total available market.

Memory

Our memory solutions deliver time-to-market, performance, power, area and economic benefits for system OEMs. Our Bandwidth Engine memory ICs integrate our proprietary, 1T-SRAM high-density embedded memory and a highly-efficient serial interface protocol resulting in a monolithic memory IC solution optimized for memory bandwidth and transaction access performance. Further performance benefits can be achieved to offload statistical, search or other custom functions using our optional integrated logic and processor elements. As discussed below, we initiated an end-of-life of these products in 2023.

Our primary focus is the development, marketing and sale of our mmWave products.

mmWave ICs

Currently, there are two industry standards that incorporate mmWave technology for wireless communications: (i) license-free: IEEE 802.11ad/ay and (ii) licensed: 3GPP Release 15-17 (commonly referred to as 5G). We have developed and continue to develop products that conform to these standards. To date, we have not sold any 5G products.

Our first mmWave IC product line operates in the license-free 60 GHz band and conforms to the IEEE 802.11ad standard. This product line includes a baseband IC, several variations of mmWave radio frequency, or RF, ICs, and associated antenna technology.

Our 60 GHz IEEE802.11ad products have two very important advantages over traditional 2.4 GHz / 5 GHz Wi-Fi products: very high data rates (up to 3.0 Gigabits per second (“Gbps”)) and low latency, i.e., less than 5 ms. The first application that had traction was outdoor broadband, including applications such as PtP backhaul links or FWA using PtMP links. As the spectrum is unlicensed (free), WISPs can provide services without having to procure expensive wireless spectrum licenses. We believe that our mmWave technology can be deployed quickly and cost effectively in rural and suburban environments, including in remote and low-income regions where residents often have poor Internet quality. While carriers can provide fiber access, the cost of fiber deployment can be prohibitive and trenching for fiber is time consuming and can limit the rate at which new subscribers are added. Our mmWave products enable WISPs to deploy broadband service using low-cost terminals and infrastructure and avoid the costs of deploying cable or fiber.

We are a leading supplier of semiconductors in the mmWave PtP and PtMP markets. We are currently shipping to leading equipment suppliers in this space, as well as directly to service providers that are building their own equipment. We believe we bring certain advantages to the market. First, our products support the spectrum from 66 GHz to 71 GHz, which is often referred to as channels 5 and 6 in the 802.11ad/ay specifications. The key advantage in supporting these channels is that the signals are able to propagate much further than channels 1 through 4; this is a result of significantly lower oxygen absorption at frequencies above 66 GHz. To date, our FWA customers have achieved links in the range of 25 kilometers, which is substantially longer than any past 60 GHz links.

In the indoor area, the 802.11ad technology is ideal for high-speed, low-latency video applications. In indoor applications, our products can support 3Gb/s links with under 5 ms of latency. Example applications include:

● AR/VR links between the headset and the video console;

● USB video cameras for corporate video conferencing;

● wireless security cameras; and

● smart factory safety and surveillance.

Our mmWave ICs have been in volume production since 2018. A core competency of the Company is phased-array technology, or beamforming, in which an array of antenna elements work in unison to create a focused RF beam. Through adjustment of the relative phase of the antenna signals, the beams can be directed to support robust wireless connection. We are a leader in the production of mmWave devices and have pioneered a high-volume mmWave production test methodology using standard low-cost production test equipment. It has taken us several years to refine performance of this production test methodology, and we believe this places us in a leadership position in addressing operational challenges of delivering mmWave products into high-volume markets.

Our second product line addresses the 5G mmWave opportunity. Given our extensive experience in the development of mmWave technology, 5G mmWave is a logical adjacent and larger market. We have commenced sampling a highly integrated 5G mmWave beamformer IC, which operates from the 24 GHz to 43 GHz frequency range. The device supports dual-stream multiple input, multiple output, or MIMO, with two 16-channel beamforming arrays. In June 2023, we announced a collaboration with pSemi, a Murata company, for the development of a 5G customer premise receiver utilizing our beamformer IC and pSemi’s up-down converter IC. The goals of the collaboration are to reduce the number of components and cost of each RF module to promote faster time to market for more rapid deployment by prospective customers.

mmWave Antenna Modules

In the second half of 2021, we augmented our business model to produce and sell complete mmWave antenna modules for license-free 60 GHz applications. The primary advantage provided by our antenna modules is that our proprietary mmWave ICs and the antenna are integrated into a single device. A differentiating characteristic of mmWave technology is that the RF amplifiers must be as close as possible to the antenna to minimize loss. With our module, we can guarantee the performance of the amplifier/antenna interface and simplify customers’ RF engineering, facilitating more opportunities for customer prospects that have not provided RF-type systems, as well as shortening the time to market for new products. It is possible for third parties to provide competitive module products, but, because we utilize our mmWave ICs and incorporate our proprietary mmWave antenna IP, we can provide a highly-competitive solution based on our internally-owned and developed module components.

During 2022, we launched our PERSPECTUS family of mmWave antenna modules to enable WISPs to offer high-capacity FWA networks in the unlicensed 60-GHz spectrum. The PERSPECTUS product family includes a new generation of integrated 60 GHz mmWave antenna modules and enhanced software for PtMP FWA applications. Our PERSPECTUS products allow rapid development of low-cost network equipment utilizing over 14 GHz of spectrum to provide multi-gigabit access services. Leveraging our integrated phased-array antennas and operating in the upper channels of the band, link ranges from 1.5 kilometers up to extended ranges of 30 kilometers can be achieved using a parabolic reflector.

Additionally, we have established an innovative user arbitration protocol called DUNE that is specifically designed to optimize network performance in dense urban environments using our PERSPECTUS antenna modules. DUNE is a result of our decade-long experience in mmWave technology and in-house development of the intellectual property incorporated in media access control, which controls the hardware, the physical layer, which controls the physical connection and software drivers, as well as novel antenna designs and beamforming algorithms. DUNE takes a multi-level approach to reducing contention and interference by incorporating both physical, e.g. antenna and beamforming, and protocol-level innovations.

Memory

Our memory products comprise our Bandwidth Engine ICs, which are memory-dominated ICs that were designed to be i) high-performance companion ICs to packet processors and ii) targeted for high-performance applications where throughput is critical. These products integrate our proprietary, 1T-SRAM high-density embedded memory and a highly-efficient serial interface protocol resulting in a monolithic memory IC solution optimized for memory bandwidth and transaction access performance. Taiwan Semiconductor Manufacturing Corporation, or TSMC, is the sole foundry that manufactures the wafers used to produce our memory IC products. TSMC has informed us that it would be discontinuing the foundry process used to produce wafers, in turn, necessary to manufacture our memory ICs. As a result, in May 2023, we initiated an end-of-life, or EOL, of our memory IC products. We notified our customers to provide purchase orders by December 22, 2023, and we commenced initial EOL shipments during the quarter ended September 30, 2023. We have requested customers to pay a deposit upon purchase order placement to reserve supply and provide funding for our required inventory purchases. In addition, we have requested customers to accelerate payments to improve our cash flows. Under our EOL plan, we expect shipments of our memory products to continue until at least December 31, 2024. However, the timing of EOL shipments will be dependent on receipt of purchase orders from customers, deliveries from our suppliers, and the delivery schedules requested by our customers. As of March 1, 2024, we have received EOL purchase orders totaling approximately $14.0 million, of which $3.7 million of these orders were shipped during 2023.

Our ability to compete in the future depends on successfully improving our technology to meet the increasing demand for higher performance and lower cost solutions. Development of new IC products requires specialized chip design and product engineers, expensive computer-aided design software licenses, and significant fabrication and testing costs, including mask costs.

We have over 14 years of technical know-how in the design and manufacturing of mmWave technology. The most important aspect of this knowledge is knowing how mmWave circuits will perform in a real-world environment. Traditionally, semiconductor design utilizes sophisticated computer-aided design software to simulate the performance of a device that is manufactured at a specific semiconductor manufacturing plant. However, mmWave is extremely difficult to model precisely. Therefore, the only path to understand how well a device will perform is to produce the device and test it in a real-world application. Over the last decade, many companies have attempted to develop mmWave semiconductor devices, however, given that the devices had inconsistent or weak performance, a number of the companies were unsuccessful and abandoned their design and product development efforts. As an example of our leadership and expertise in the development of mmWave technology, we were an active participant in the development of the IEEE 802.11ay wireless specification and, to date, have been granted nine essential claims patents with respect to this standard.

At a system level, there are additional technical challenges presented by mmWave technology that we have overcome and form a key part of our internal know-how. For example, a key technology of mmWave is the concept of beamforming and beam steering using a phased-array antenna. This technology is utilized to concentrate the RF energy into a narrow beam to improve the range and coverage of mmWave devices. We have developed effective beamforming and beam steering technology for phased-array circuits and antennas. While there are many academic examples of successful phased-array implementations, there is a vast barrier between a “laboratory” version of phased-array technology and a version that is deployed for commercial use. One such aspect is the implementation of the beamforming procedure, which seeks to maximize throughput and do so while not impacting latency. While the details of achieving this are complex, it is important-intellectual property that we have gained through real-world experience.

mmWave is not without challenges, as mmWave signals do not typically travel as far as traditional wireless signals and are more attenuated by solid objects. Mitigation strategies must be deployed, particularly with regard to the management of signal propagation. Whereas traditional wireless devices utilize a broad, omni-antenna pattern, mmWave systems rely on phased-array technology, which focusses the radio signal into a narrow beam to improve propagation characteristics. We consider ourselves to be a global leader in implementing these sophisticated radio systems and one of the few providers in the market successfully shipping phased-array devices in mass production.

While we have developed products for the 60 GHz and 5G mmWave markets, we believe there are other market opportunities that could utilize mmWave technology. For example, in the WiFi Alliance there is a pending proposal to utilize mmWave technology in WiFi 8, which is the next generation of WiFi technology. We believe this proposal is primarily driven by the anticipated use of mmWave to support VR applications, which require very high data rates, and to reduce congestion in multi-dwelling units. In the mobile carrier market, there is some early research in the use of terahertz technology to make even more spectrum available for network capacity. While the proposed frequencies are higher than mmWave (above 100 GHz), we believe that many of our technological developments, particularly our beamforming and beamsteering concepts, can be applied to terahertz technology.

With regard to our memory products, we have ceased and do not intend to expend any development efforts or funds to develop new memory products. We believe our Bandwidth Engine IC products will provide us with meaningful revenue and gross margin contributions through at least the end of 2024, as we complete the EOL of these products. We intend to continue to devote substantially all of our research and development efforts toward further expanding our mmWave technology portfolio and expanding our product offerings.

In addition to our direct sales personnel, we sell through sales representatives and distributors in the United States, Asia and Europe. Our distributors have a global presence with offices and technical selling and applications engineering capabilities, which we believe will enable us to reach new potential customers for our products.

We also have applications engineers who support our customer engagements and engage with the customers’ system architects and designers to propose and implement our products and solutions to address system design challenges and improve performance.

In the markets we serve, the time from a design win to production volume shipments of our IC products can range from 12 to 36 months. We believe that networking, wireless and wired communication and security appliance systems can have a product life from a few years to over 10 years once a product like ours has been designed into the system. Historically, our revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue.

In the FWA market, our primary customer base is OEMs, but we also have multiple WISP customers in the U.S. and Canada. Our OEM customers in the fixed wireless space include Ubiquiti, WeLink, which operates as both an OEM and a WISP, Tachyon Networks, or Tachyon, and China Unicom. Ubiquiti, an OEM in the unlicensed fixed wireless space, relies on us as its sole source mmWave IC supplier for its “Wave” products, which Ubiquiti introduced in 2022. Ubiquiti introduced three new Wave models in 2023. WeLink has relied on us as its sole source supplier for WeLink designed equipment used to deliver WISP residential service since 2022. WeLink currently deploys 60 GHz technology in multiple U.S. cities, including Las Vegas, Dallas and Los Angeles. Tachyon utilizes our mmWave antenna modules in its TNA-30X family of PtP and PtMP solutions for 60 GHz unlicensed FWA networks. Peraso and Tachyon jointly announced production readiness of the TNA-30X product family in June 2023. Finally, China Unicom is a Chinese mobile carrier that uses our 60 GHz technology for 5G PtP backhaul. In addition to OEMs, we have partnered with several WISPs in the U.S. and Canada that have deployed our 60 GHz technology, including WeLink. We continue to focus on securing new OEM and WISP customers.

During the year ended December 31, 2023, three customers accounted for 10% or more of our net revenues, including Nokia Corporation at 35%, F5/Flextronics at 22% and Alltek Technology Corp at 18%. During the year ended December 31, 2022, four customers accounted for 10% or more of our net revenues, including Nokia Corporation at 26%, WeLink Communications LLC, or WeLink, at 21%, CEAC International Limited, or CEAC, a distributer selling to Ubiquiti, at 16%, and F5, Inc. at 11%.

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of March 1, 2024, we held 96 United States patents and 67 foreign patents on various aspects of our mmWave, antenna, memory and other technology, with expiration dates ranging from 2025 to 2041. We also held 13 pending patent applications in the United States and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

We were also an active participant in the development of the IEEE 802.11ay wireless specification and, to date, have been granted nine essential claims patents with respect to this standard. Essential claims patents are of particular value as a specification cannot be implemented without obtaining a license to the patents from us.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our IC customers, licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, “Risk Factors.”

mmWave

mmWave circuit and system design is a highly specialized engineering skill, as mmWave is a challenging technology to ship in mass production. At frequencies above 24 GHz, circuits are extremely vulnerable to small variances in the semiconductor manufacturing process. Designing circuits that minimize susceptibility to these variances takes years of development, and we believe we are one of the few companies in the world that is skilled in mmWave design. Further, we have shipped mmWave devices in volume, and ensuring all devices sold adhere to strict performance standards is a core competency we have developed. In addition, we have developed our own mmWave phased-array antenna technology, which allows us to be highly competitive in terms of overall system cost. Our customers do not need to engage with third-party antenna suppliers, thus eliminating the additional cost for a third-party antenna.

Unlicensed IEEE 802.11ad/ay Market:

Our primary competitor in the IEEE802.11ad/ay market is Qualcomm. The primary benefit that we provide to the market is the support of the higher frequency bands from 66 GHz to 71 GHz. The advantage at these frequencies is that oxygen attenuation is significantly reduced, and signals can travel much further.

We also have key points of differentiation compared to Qualcomm for wireless video devices. We are well positioned in this market, as we have USB 3.0 built into our devices, so our products generally support USB architectures. A prime example is the replacement of the USB cable with a wireless version using our technology. There are many applications where this can be of use, including USB web cams, wireless displays, and AR/VR headsets. We have invested significant software resources into providing the market with wireless USB solutions, and we believe there is no other mmWave vendor in the world that can offer multi-gigabit solutions as a replacement for wired USB.

Licensed 5G Market:

With 5G, our efforts are focused on the mmWave RF front-end phased-array component of the system. The 5G product instantiation is an RF module utilizing our proprietary intellectual property. Key elements of our mmWave intellectual property include:

● RF circuits;

● phased-array antenna; and

● in-system circuit calibration, beam forming, and real-time system monitoring.

From a competitive perspective, we believe we are currently the only pure-play, 5G vendor to offer a dual-band (28/39 GHz) RF solution for the FWA market. Qualcomm does offer a 5G RF solution for the FWA market, however its solution is based on aggregating its mobile RF solution, which we believe requires several compromises in terms of cost, performance, and power consumption. With an initial focus on FWA, we can derive advantages by optimizing our silicon for that specific market. Furthermore, we have achieved traction in the unlicensed, 60 GHz, FWA market, and we believe we will be able to transfer all of our knowledge gained from the 60 GHz market to the 5G market. However, this market opportunity is more competitive, and potential competitors, in addition to Qualcomm, include MediaTek Inc. and Samsung Electronics Co., Ltd.

We depend on third-party vendors to manufacture, package, assemble and test our IC and module products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility. By outsourcing manufacturing, we can avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

We perform an ongoing review of our product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meets design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers.

As of December 31, 2023, we had 48 employees, including 13 located in the United States and 35 located in Canada. Our headcount consisted of 34 in research and development and manufacturing-related operations and 14 in sales, marketing and general and administrative functions. These headcount amounts exclude employees in Canada that were placed on temporary lay-off in November 2023. We believe our current headcount is adequate to conduct our business.

We were founded in 1991 and reincorporated in Delaware in 2000. Our website address is www.perasoinc.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Exchange Act, as soon as reasonably practicable after they are filed with, or furnished to, the SEC. You can also read any materials submitted electronically by us to the SEC on its website (www.sec.gov), which contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Peraso Inc., together with its subsidiaries (“Peraso,” the “Company,” “we,” “our” or “us”), is a fabless semiconductor company focused on the development and sale of: i) semiconductor devices and millimeter wavelength wireless technology, or mmWave antenna modules based on its proprietary semiconductor devices and ii) performance of non-recurring engineering, or NRE, services and licensing of intellectual property, or IP. Our primary focus is the development of mmWave, which is generally described as the frequency band from 24 Gigahertz, or GHz, to 300GHz. Our mmWave products enable a range of applications, including i) multi-gigabit point-to-point, or PtP, wireless links with a range of up to 25 kilometers and operating in the 60Ghz frequency band, ii) multi-gigabit point-to-multi-point, or PtMP, links in the 60GHz frequency band used to provide fixed wireless access, or FWA, services, iii) FWA in the 5G operating bands from 24GHz to 43GHz to provide multi-gigabit capability and low latency connections, and iv) consumer applications, such as wireless video streaming and untethered augmented reality and virtual reality, or AR/VR. We also have a line of memory-denominated integrated circuits, or ICs, for high-speed cloud networking, communications, security appliance, video, monitor and test, data center and computing markets that deliver time-to-market, performance, power, area and economic benefits for system original equipment manufacturers, or OEMs.

We were formerly known as MoSys, Inc., or MoSys. On September 14, 2021, we and our subsidiaries, 2864552 Ontario Inc. and 2864555 Ontario Inc., entered into an Arrangement Agreement, or the Arrangement Agreement, with Peraso Technologies Inc., or Peraso Tech, a privately-held corporation existing under the laws of the province of Ontario, to acquire all of the issued and outstanding common shares of Peraso Tech, or the Peraso Shares, including those Peraso Shares to be issued in connection with the conversion or exchange of secured convertible debentures and common share purchase warrants of Peraso Tech, as applicable, by way of a statutory plan of arrangement, or the Arrangement, under the Business Corporations Act (Ontario). On December 17, 2021, following the satisfaction of the closing conditions set forth in the Arrangement Agreement, the Arrangement was completed, and we changed our name from MoSys to “Peraso Inc.” and began trading on The Nasdaq Stock Market, or the Nasdaq, under the symbol “PRSO.” Certain previous shareholders of Peraso Tech elected to convert their Peraso Tech common stock into exchangeable shares in 2864555 Ontario Inc., one of our wholly-owned subsidiaries. These exchangeable shares, which can be converted into our common stock at the option of the holder, are similar in substance to our common stock.

The demand for wireless services is increasing exponentially, and, as a result, the current low frequency spectrum (under 7GHz) is running out of capacity. While service providers have maximized the capacity of the available spectrum, demand continues to outpace supply. We believe that mmWave spectrum will need to be utilized.

MmWave has been standardized for use in both licensed and unlicensed applications. In the licensed market, the 3rd Generation Partnership Project, or 3GPP, standards organizations have included mmWave frequencies in the 5G specification, utilizing the frequency band from 24GHz to 43GHz. The Institute of Electrical and Electronics Engineers, or IEEE, has standardized mmWave in the unlicensed band from 57GHz to 71GHz. We believe mmWave will soon be licensed on the 45GHz band in China.

A primary opportunity for the unlicensed product line is the FWA market. This market is primarily driven by wireless Internet service providers, or WISPs, in contrast to the licensed market, which is primarily serviced by large telecommunications carriers such as AT&T, Verizon and T-Mobile. Pursuant to the 2022 Fixed Wireless Access and Infrastructure and Devices report issued in September 2022 by Mobile Experts Inc., the WISP market has been estimated to be 3.2M subscribers in 2023. The market is primarily served today by traditional WiFi technology using the 2.4GHz and 5GHz bands. From an equipment perspective, this worldwide market is historically serviced by FWA original equipment manufacturers, or OEMs, such as Ubiquiti Inc., Cambium Networks, Ltd. and SIA MikroTik. WISPs are addressing a segment of the broadband market not served by the traditional carriers, or, in some cases, underserved by the carriers.

This market has been helped in recent years with the advent of government incentives aimed at closing the so-called ‘digital divide’ between urban and rural broadband access. In the United States, such incentive programs include the Regional Digital Opportunity Fund, or RDOF, the Broadband Equity, Access and Deployment, or BEAD, Program, and the Affordable Connectivity Program. However, in addition to rural markets, WISPs have begun offering services in large urban markets in the United States, such as Las Vegas, Los Angeles and Phoenix. The basic business premise is that the 60GHz spectrum is free, and WISPs can pass this cost savings on the customer and compete with more traditional Internet access services, such as cable broadband or digital subscriber line, or DSL.

There are several other market opportunities for 60GHz mmWave technology. Such market opportunities include transportation safety, factory automation, military, and railway communications.

Our 60GHz products can also be applied to consumer applications, as our technology can provide key advantages to this market. For example, the data rates of our Versatus antenna module product is 3Gbps, which is a good fit for high performance, 4K video for VR applications. Additionally, VR requires very low latency; under 5ms. Another benefit of 60GHz in the VR market, and in the streaming video market, is low interference. A primary characteristic of mmWave technology is the use of beamforming, which focuses the radio frequency, or RF, energy into a narrow beam. Not only does this provide improved range, it also provides physical isolation from other transmitters, and leads to reduced interference versus traditional wireless technology. Other high performance video applications include streaming, docking, surveillance, and AR.

Considering the licensed 5G market, there are several primary applications for mmWave. Our initial target is the FWA segment. In this market segment, carriers provide their customers with a fixed wireless link to a base station or small cell, thus providing the customer with high-speed access to the Internet. mmWave can provide download speeds of over 1 Gbps and upload speeds of several hundred megabits per second. In addition, mmWave is a much cheaper alternative to installing fiber and allows carriers an additional advantage and competitive advantage against other access technologies, such as cable broadband. Additionally, our mmWave antenna modules can be utilized in consumer-premise applications, including hotspots, laptops and tablets. 5G mmWave has support from major industry players. Apple has incorporated mmWave wireless into substantially all versions of the iPhone for sale in the US market. The basic premise is the ever-increasing demand for bandwidth. Verizon is the leading carrier in the US at deploying mmWave for both mobile and fixed wireless access. The initial use case for cellular service providers is to provide their customer base (primarily smart-phone customers) with continuity of network access in highly congested environments, such as sporting events, public beaches, music festivals or generally any large gathering where thousands of users are attempting to access the network simultaneously. We believe that mmWave will gain universal acceptance, as users will demand full continuity in terms of network access, and we are well positioned to address the mobile opportunity for mmWave, which is expected to present an order of magnitude increase in the total available market.

mmWave is not without challenges, as mmWave signals do not typically travel as far as traditional wireless signals and are more attenuated by solid objects. Mitigation strategies must be deployed, particularly with regard to the management of signal propagation. Whereas traditional wireless devices utilize a broad, omni-antenna pattern, mmWave systems rely on phased array technology, which focusses the radio signal into a narrow beam to improve propagation characteristics. Peraso is a global leader in implementing these sophisticated radio systems and is one of the few companies in the market that is successfully shipping phased array devices in mass production.

Memory

Our memory solutions deliver time-to-market, performance, power, area and economic benefits for system original equipment manufacturers, or OEMs. Our primary product line is marketed under the Accelerator Engine name and comprises our Bandwidth Engine and quad-partition rate SRAM memory ICs, which integrate our proprietary, 1T-SRAM high-density embedded memory and a highly-efficient serial interface protocol resulting in a monolithic memory IC solution optimized for memory bandwidth and transaction access performance. Further performance benefits can be achieved to offload statistical, search or other custom functions using our optional integrated logic and processor elements.

As data rates and the amount of high-speed processing increase, critical memory access bottlenecks occur. Our Accelerator Engine ICs dramatically increase memory accesses per second, removing these bottlenecks. In addition, the serial interface and high-memory capacity reduce the board footprint, number of pins and complexity, while using less power.

Our primary focus is the development, marketing and sale of our mmWave products. Currently, there are two industry standards that incorporate mmWave technology for wireless communications: (i) IEEE 802.11ad/ay and (ii) 3GPP Release 15-17 (commonly referred to as 5G). We have developed and continue to develop products that conform to these standards. To date, we have not sold any 5G products.

mmWave ICs

Our first mmWave product line operates in the 60 GHz band and conforms to the IEEE 802.11ad standard. This product line includes a baseband IC, several variations of mmWave radio frequency, or RF, ICs, as well as associated antenna technology. The second product line addresses the 5G mmWave opportunity. Given our extensive experience in the development of mmWave technology, 5G mmWave, is a logical adjacent and larger market.

Our initial target market was the 60GHz IEEE 802.11ad market. Our 60GHz IEEE802.11ad products had two very important advantages over traditional 2.4GHz / 5GHz Wi-Fi products: very high data rates (up to 4.5 Gigabits per second, or Gb/s) and low latency, i.e., less than 5 milliseconds, or ms. The first application that had traction was outdoor broadband, including applications such as point-to-point, or PtP, backhaul links or FWA using point-to-multipoint, or PtMP, links. As the spectrum is unlicensed (free), wireless carriers can provide services without having to spend significantly on wireless spectrum licenses. These services are offered by WISPs. The WISP market has seen significant growth over the last six years. In the United States, the number of subscribers that WISP providers serve has grown from 4 million in 2016 to 6.7 million in 2022 and could grow to 12.7 million subscribers in 2025, based on The 2021 Fixed-Wireless and Hybrid ISP Industry Report prepared by the Carmel Group.

We are a leading supplier of semiconductors in the PtP and PtMP markets. We are currently shipping to leading equipment suppliers in this space, as well as directly to service providers that are building their own equipment. We believe we bring certain advantages to the market. First, our products support the spectrum from 66 GHz to 71GHz. These are often referred to as channels 5 and 6 in the 802.11ad/ay specifications. The key advantage in supporting these channels is that the signals are able to propagate much further than channels 1 through 4; this is a result of significantly lower oxygen absorption at frequencies above 66GHz. To date, our FWA customers have achieved links in the range of 25 kilometers, which is substantially longer than any past 60 GHz links.

In the indoor area, the 802.11ad technology is ideal for high-speed, low-latency video applications. In indoor applications, our products can support 3Gb/s links with under 5ms of latency. Example applications include:

● AR/VR links between the headset and the video console;

● USB video cameras for corporate video conferencing;

● wireless security cameras; and

● smart factory safety and surveillance.

We are a leader in the production of mmWave devices and have pioneered a high-volume mmWave production test methodology using standard low-cost production test equipment. It has taken us several years to refine performance of this production test methodology, and we believe this places us in a leadership position to address the operational challenge of delivering mmWave products into high-volume markets.

mmWave Antenna Modules

In the second half of 2021, we augmented our business model to produce and sell complete mmWave antenna modules. The primary advantage provided by our antenna modules is that our proprietary mmWave ICs and the antenna are integrated into a single device. A differentiating characteristic of mmWave technology is that the RF amplifiers must be as close as possible to the antenna to minimize loss. By providing a module, we can guarantee the performance of the amplifier/antenna interface and simplify our customer’s RF design engineering, facilitating more opportunities for new companies that have not provided RF-type systems, as well as shortening the time to market for new products. It is possible for third parties to provide competitive module products, but, because we utilize our mmWave ICs and incorporate our proprietary mmWave antenna IP, we can provide a highly-competitive solution based on our internally-owned and developed module components.

During 2022, we launched our PERSPECTUS family of mmWave antenna modules to enable WISPs to offer high-capacity FWA networks in the unlicensed 60-GHz spectrum. The PERSPECTUS product family includes a new generation of integrated 60-GHz mmWave antenna modules and enhanced software for PtMP FWA applications. Our PERSPECTUS products allow rapid development of low-cost network equipment utilizing over 14 GHz of spectrum to provide multi-gigabit access services. Leveraging our integrated phased-array antennas and operating in the upper channels of the band, link ranges from 1.5 kilometers up to extended ranges of 30 kilometers can be achieved using a parabolic reflector.

Memory

Accelerator Engines

Our memory products comprise our Accelerator Engine ICs, which include our Bandwidth Engine and quad-partition rate SRAM memory ICs.

Bandwidth Engine

The Bandwidth Engine is a memory-dominated IC that was designed to be a high-performance companion IC to packet processors and is targeted for high-performance applications where throughput is critical. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element. Our Bandwidth Engine ICs combine: (1) our proprietary high-density, high-speed, low latency embedded memory, (2) our high-speed serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM memory and serial interface with logic and other intelligence functions provides a system-level solution and significantly improves overall system performance at lower cost, size and power consumption. Our Bandwidth Engine ICs can provide up to and over 6.5 billion memory accesses per second externally and 12 billion memory accesses per second internally, which we believe is more than three times the performance of current memory-based solutions. They also can enable system designers to significantly narrow the gap between processor and memory IC performance. Our customers that design Bandwidth Engine ICs onto the line cards in their systems will re-architect their systems at the line-card level and use our product to replace traditional memory IC solutions, such as dynamic random access, or DRAM, and static random access memory, or SRAM, ICs. When compared with existing commercially available DRAM and SRAM IC solutions, our Bandwidth Engine ICs may:

● provide up to four times the performance;

● reduce power consumption by approximately 50%;

● reduce cost by greater than 50%; and

● result in a dramatic reduction in IC pin counts on the line card.

Our Bandwidth Engine 2 IC products contain 576 megabits, or Mb, of memory and use a SerDes interface with up to 16 lanes operating at up to 12.5 Gbps per lane. We have been shipping our Bandwidth Engine 2 IC products since 2013.

Our Bandwidth Engine 3 IC products contain 1152 Mb of memory and use a SerDes interface with up to 16 lanes operating at up to 25 Gbps per lane. Our Bandwidth Engine 3 ICs target support for packet-processing applications with up to five billion memory single word accesses per second, as well as burst mode to enable full duplex buffering up to 400 Gbps for ingress, egress and oversubscription applications. The devices provide benefits of size, power, pin count, and cost savings to our customers.

QPR

Our quad partition rate, or QPR, family of low cost, ultra-high speed SRAM memory devices are optimized for FPGA-based systems. Our QPR memory technology features an architecture that allows for parallel accesses to multiple partitions of the memory simultaneously and allows access of up to 576 bits per read or write cycle. The QPR device includes four independent partitions per input/output and each partition functions as a stand-alone random-access SRAM. The high-performance interface, larger density and the multiple partitions work together to support multiple independent functional blocks within an FPGA with one QPR device. Our MSQ220 and MSQ230 QPR devices are ideally suited for random-access applications.

Our ability to compete in the future depends on successfully improving our technology to meet the increasing demand for higher performance and lower cost solutions. Development of new IC products requires specialized chip design and product engineers, expensive computer-aided design software licenses, and significant fabrication and testing costs, including mask costs.

We have over 14 years of technical know-how in the design and manufacturing of mmWave technology. The most important aspect of this knowledge is knowing how mmWave circuits will perform in a real-world environment. Traditionally, semiconductor design utilizes sophisticated computer-aided design software to simulate the performance of a device that is manufactured at a specific semiconductor manufacturing plant. However, mmWave is extremely difficult to model precisely. Therefore, the only path to understand how well a device will perform is to produce the device and test it in a real-world application. Over the last decade, many companies have attempted to develop mmWave semiconductor devices, however, given that the devices had inconsistent or weak performance, a number of the companies were unsuccessful and abandoned their design and product development efforts. As an example of our leadership and expertise in the development of mmWave technology, we were an active participant in the development of the IEEE 802.11ay wireless specification and, to date, have been granted nine essential claims patents with respect to this standard.

At a system level, there are additional technical challenges presented by mmWave technology that we have overcome and form a key part of our internal know-how. For example, a key technology of mmWave is the concept of beamforming and beam steering using a phased array antenna. This technology is utilized to concentrate the RF energy into a narrow beam to improve the range and coverage of mmWave devices. We have developed effective beamforming and beam steering technology for phased array circuits and antennas. While there are many academic examples of successful phased array implementations, there is a vast barrier between a “laboratory” version of phased array technology and a version that is deployed for commercial use. One such aspect is the implementation of the beamforming procedure, which seeks to maximize throughput and do so while not impacting latency. While the details of achieving this are complex, it is important-intellectual property that we have gained through real-world experience.

With regard to our memory products, we do not have internal resources to develop new, memory IC products, and do not intend to expend any development efforts or funds to develop new memory products. That said, we believe our Accelerator Engine IC products will provide us with meaningful revenue and gross margin contributions through at least the end of 2024. We intend to continue to devote substantially all of our research and development efforts toward further expanding our mmWave technology portfolio and expanding our product offerings.

In addition to our direct sales personnel, we sell through sales representatives and distributors in the United States, Asia and Europe. Our distributors have a global presence with offices and technical selling and applications engineering capabilities, which we believe will enable us to reach new potential customers for our products.

We also have applications engineers who support our customer engagements and engage with the customers’ system architects and designers to propose and implement our products and solutions to address system design challenges and improve performance.

In the markets we serve, the time from a design win to production volume shipments of our IC products can range from 12 to 36 months. Networking, wireless and wired communication and security appliance systems can have a product life from a few years to over 10 years once a product like ours has been designed into the system. Historically, our revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue.

During the year ended December 31, 2022, four customers accounted for 10% or more of our net revenues, including Nokia Corporation at 26%, WeLink Communications LLC, or WeLink, at 21%, CEAC International Limited, or CEAC, a distributer selling to Ubiquiti Inc., at 16%, and F5, Inc. at 11%. During the year ended December 31, 2021, three customers accounted for 10% or more of our net revenues, including CEAC at 48%, WeLink at 19% and Alltek Technology Corp., a distributer selling to Ubiquiti Inc., at 11%.

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of December 31, 2022, we held 95 United States patents and 59 foreign patents on various aspects of our mmWave, antenna, memory and other technology, with expiration dates ranging from 2025 to 2041. We also held 15 pending patent applications in the United States and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

We were also an active participant in the development of the IEEE 802.11ay wireless specification and, to date, have been granted nine essential claims patents with respect to this standard. Essential claims patents are of particular value as a specification cannot be implemented without obtaining a license to the patents from us.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our IC customers, licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, “Risk Factors.”

mmWave

mmWave circuit and system design is a highly specialized engineering skill, as mmWave is a challenging technology to ship in mass production. At frequencies above 24GHz, circuits are extremely vulnerable to small variances in the semiconductor manufacturing process. Designing circuits that minimize susceptibility to these variances takes years of development, and we believe we are one of the few companies in the world that is skilled in mmWave design. Further, we have shipped mmWave devices in volume, and ensuring all devices sold adhere to strict performance standards is a core competency we have developed. In addition, we have developed our own mmWave phased array antenna technology, which allows us to be highly competitive in terms of overall system cost. Our customers do not need to engage with third-party antenna suppliers, thus eliminating the additional cost for a third-party antenna.

Unlicensed IEEE 802.11ad/ay Market:

Our primary competitor in the IEEE802.11ad/ay market is Qualcomm. The primary benefit that we provide to the market is the support of the higher frequency bands from 66GHz to 71GHz. The advantage at these frequencies is that oxygen attenuation is significantly reduced, and signals can travel much further.

We also have key points of differentiation compared to Qualcomm for wireless video devices. We are well positioned in this market, as we have USB 3.0 built into our devices, so our products generally support USB architectures. A prime example is the replacement of the USB cable with a wireless version using our technology. There are many applications where this can be of use, including USB web cams, wireless displays, and AR/VR headsets. We have invested significant software resources into providing the market with wireless USB solutions, and we believe there is no other mmWave vendor in the world that can offer multi-gigabit solutions as a replacement for wired USB.

Licensed 5G Market:

With 5G, our efforts are focused on the mmWave RF front-end phased array component of the system. The 5G product instantiation is an RF module utilizing our proprietary intellectual property. Key elements of our mmWave intellectual property include:

● RF circuits;

● phased-array antenna; and

● in-system circuit calibration, beam forming, real-time system monitoring.

From a competitive perspective, we believe we are currently the only pure-play, 5G vendor to offer a dual-band (28/39GHz) RF solution for the FWA market. Qualcomm does offer a 5G RF solution for the FWA market, however its solution is based on aggregating its mobile RF solution, which requires several compromises in terms of cost, performance, and power consumption. With an initial focus on fixed wireless access, we can derive advantages by optimizing our silicon for that specific market. Furthermore, we have achieved traction in the unlicensed, 60GHz, FWA market, and we believe we will be able to transfer all of our knowledge gained from the 60GHz market to the 5G market. However, this market opportunity is more competitive, and potential competitors, in addition to Qualcomm, include MediaTek Inc. and Samsung Electronics Co., Ltd., or Samsung.

Memory

The markets for our memory products are highly competitive. We believe that the principal competitive factors are:

● processing speed and performance; ● density and cost; ● power consumption; ● reliability; ● interface requirements; ● ease with which technology can be customized for and incorporated into customers’ products; and ● level of technical support provided.

We believe that our products compete favorably with respect to each of these criteria. Our proprietary 1T-SRAM embedded memory and high-speed serial interface IP can provide our Accelerator Engine ICs with a competitive advantage over alternative devices. Our Accelerator Engine ICs compete with embedded memory solutions, stand-alone memory ICs, including both DRAM and SRAM ICs, application-specific, or ASICs, designed by customers in-house to meet their system requirements, and network processing units, or NPUs, that use significant internal memory and customer-designed software to implement tasks. Competitive DRAM solutions primarily include RLDRAM from Micron Technology, Inc., or Micron, LLDRAM from Renesas, DDR from Samsung, Micron and others, and high-bandwidth memory, or HBM, which is stacked DRAM memory from Samsung and SK Hynix. SRAM solutions can meet high-speed performance requirements, but often lack adequate memory size. Competitive SRAM solutions primarily include QDR or similar SRAM products from Infineon Technologies AG and GSI Technology, Inc. Most of the currently available SRAM and DRAM solutions use a parallel, rather than a serial interface. To offset these drawbacks, system designers generally must use more discrete memory ICs, resulting in higher power consumption and greater utilization of space. Our competitors include established semiconductor companies with significantly longer operating histories, greater name recognition and reputation, large customer bases, dedicated manufacturing facilities and greater financial, technical, sales and marketing resources. This may allow them to respond more quickly than us to new or emerging technologies or changes in customer requirements. Generally, customers prefer suppliers with greater financial resources than we have currently. Many of our competitors also have significant influence in the semiconductor industry. They may be able to introduce new technologies or devote greater resources to the development, marketing and sales of their products than we can. Furthermore, in the event of a manufacturing capacity shortage, these competitors may be able to manufacture products when we are unable to do so.

We depend on third-party vendors to manufacture, package, assemble and test our IC and module products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility. By outsourcing manufacturing, we can avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

We perform an ongoing review of our product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meets design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers.

As of December 31, 2022, we had 73 employees, including 17 located in the United States and 56 located in Canada. Our headcount consisted of 54 in research and development and manufacturing operations and 19 in sales, marketing and general and administrative functions. In February 2023, we implemented a reduction in our workforce and eliminated five positions. We believe our current headcount is adequate to conduct our business.

We were founded in 1991 and reincorporated in Delaware in 2000. Our website address is www.perasoinc.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Exchange Act, as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read any materials submitted electronically by us to the SEC on its website (www.sec.gov), which contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Overview

Peraso Inc., together with its subsidiaries (“Peraso,” the “Company,” “we,” “our” or “us”), is a fabless semiconductor company focused on the development and sale of: i) semiconductor devices and modules based on our proprietary semiconductor devices and ii) performance of non-recurring engineering, or NRE, services and licensing of intellectual property, or IP. Our primary focus is the development of millimeter wavelength, or mmWave, wireless technology, for the 60 Gigahertz, or GHz, spectrum and for 5G cellular networks, or 5G. Our mmWave products enable a range of applications, such as 5G with low latency and high reliability, as well as multi-gigabit, mmWave links over 25 kilometers. Our mmWave products address consumer applications, such as wireless video streaming and untethered augmented reality and virtual reality, or AR/VR. We also have a line of memory-denominated integrated circuits for high-speed cloud networking, communications, security appliance, video, monitor and test, data center and computing markets that deliver time-to-market, performance, power, area and economic benefits for system original equipment manufacturers, or OEMs.

We were formerly known as MoSys, Inc., or MoSys. On September 14, 2021, we and our subsidiaries, 2864552 Ontario Inc. and 2864555 Ontario Inc., entered into an Arrangement Agreement, or the Arrangement Agreement, with Peraso Technologies Inc., or Peraso Tech, a privately-held corporation existing under the laws of the province of Ontario, to acquire all of the issued and outstanding common shares of Peraso Tech, or the Peraso Shares, including those Peraso Shares to be issued in connection with the conversion or exchange of secured convertible debentures and common share purchase warrants of Peraso Tech, as applicable, by way of a statutory plan of arrangement, or the Arrangement, under the Business Corporations Act (Ontario). On December 17, 2021, following the satisfaction of the closing conditions set forth in the Arrangement Agreement, the Arrangement was completed and we changed our name from MoSys to “Peraso Inc.” and began trading on the Nasdaq Stock Market, or the Nasdaq, under the symbol “PRSO.”

Industry Trends and Performance

MMWave and 5G

The demand for wireless services is increasing exponentially, therefore, wireless users and service providers will be required to eventually utilize higher frequency spectrum to meet the demand. We believe the 5G wireless industry is the best and latest example of how and why mmWave is the future of wireless networks. The 5G specification includes low, mid and mmWave frequencies. There are significant expectations that 5G will significantly improve cellular network performance, as evidence by slogans as “10X the bandwidth” and “10X reduction in latency.” From our perspective, in reality, only part of the 5G specification truly offers such improvement, and we believe this is represented by mmWave.

mmWave is not without challenges, as mmWave signals do not typically travel as far as traditional wireless signals and are more attenuated by solid objects. Mitigation strategies must be deployed, in particular with regards to the management of signal propagation. Whereas traditional wireless devices utilize a broad, omni-antenna pattern, mmWave systems rely on phased array technology, which focusses the radio signal into a narrow beam to improve propagation characteristics. Peraso is a global leader in implementing these sophisticated radio systems and is one of the few companies in the market that is successfully shipping phased array devices in mass production.

In terms of specific market opportunity, mmWave is a key differentiating update from 4G/LTE networks to 5G. Within the 5G market, there are several primary applications for mmWave. The initial target for Peraso is referred to as the fixed wireless access, or FWA, segment. In this market segment, carriers provide their customers with a fixed wireless link to a base station or small cell, thus providing the customer with high-speed access to the Internet. mmWave can provide download speeds of over 1 Gbps and upload speeds of several hundred megabits per second. In addition, mmWave is a much cheaper alternative to fiber and allows carriers an additional advantage and competitive advantage against other access technologies, such as cable. Additionally, Peraso 5G mmWave RF modules can be utilized in other applications, including hotspots, laptops and tablets.

5G mmWave has support from major industry players. Apple has incorporated mmWave wireless into all versions of the iPhone12 for sale in the US market. The basic premise is common, which is the ever-increasing demand for bandwidth. Verizon is the leading carrier in the US at deploying mmWave for both mobile and fixed wireless access. The initial use case for cellular service providers is to provide their customer base (primarily smart phone customers) with continuity of network access in highly congested environments, such as sporting events, public beaches, music festivals or generally any large gathering where thousands of users are attempting to access the network simultaneously. Peraso believes that mmWave will gain universal acceptance, as users will demand full continuity in terms of network access.

Below are some early examples of carriers deploying mmWave technology:

• May 9, 2021: Major Japanese carriers, including NTT DOCOMO, KDDI, Rakuten and SoftBank deploy mmWave technology;

•June 8, 2021: UScellular sets record with 5G mmWave links of 10 kilometers;

• June 9, 2021: the United States Department of Defense announces use of 5G mmWave for secure communications;

•June 11, 2021: Verizon launches On Site, for the use of mmWave for on-premises, private 5G networks; and

• July 11, 2021: Verizon announces expansion of 5G home-internet, fixed-wireless service using mmWave spectrum.

Longer term, we believe we are well positioned to address the mobile opportunity for mmWave, which is expected to present an order of magnitude increase in the total available market.

Memory

Our memory solutions deliver time-to-market, performance, power, area and economic benefits for system original equipment manufacturers, or OEMs. Our primary product line is marketed under the Accelerator Engine name and comprises our Bandwidth Engine and Programmable HyperSpeed Engine IC products, which integrate our proprietary, 1T-SRAM high-density embedded memory and a highly-efficient serial interface protocol resulting in a monolithic memory IC solution optimized for memory bandwidth and transaction access performance. Further performance benefits can be achieved to offload statistical, search or other custom functions using our optional integrated logic and processor elements.

As data rates and the amount of high-speed processing increase, critical memory access bottlenecks occur. Our Accelerator Engine ICs dramatically increase memory accesses per second, removing these bottlenecks. In addition, the serial interface and high-memory capacity reduce the board footprint, number of pins and complexity, while using less power.

Our Products

Our primary focus is the development, marketing and sale of our mmWave products. mmWave is generally described as the frequency band from 24 GHz to 300 GHz. Currently, there are two industry standards that incorporate mmWave technology for wireless communications: (i) IEEE 802.11ad/ay and (ii) 3GPP Release 15-17 (commonly referred to as 5G). We have developed and continue to develop products that conform to these standards.

mmWave ICs

Our first product line operates in the 60 GHz band and conforms to the IEEE 802.11ad standard. This product line includes a baseband IC, including multiple variations of mmWave radio frequency, or RF, integrated circuits, or ICs, as well as associated antenna technology. The second product line is currently in development and addresses the 5G mmWave opportunity. Given our experience in the development of mmWave technology and devices, we believe 5G mmWave, is a logical adjacent market.

The first market targeted was the 60GHz IEEE 802.11ad market. Our 60GHz IEEE802.11ad products had two very important advantages over traditional 2.4GHz and 5GHz Wi-Fi products: very high data rates (up to 4.5 gigabits per second, or nGb/s) and low latency (less than 5 meters per second). The first application that had traction was outdoor broadband. This included applications such as point-to-point, or PtP, backhaul links or fixed wireless access, FWA, using point-to-multipoint links, or PtMP. products using the 60GHz band are for this market. As the spectrum is unlicensed (free), wireless carriers can provide services without having to spend significantly on wireless spectrum. We are a leading supplier of semiconductors in the PtP and PtMP markets. We are currently shipping to leading equipment suppliers in this space, as well as directly to service providers building their own equipment. We believe our products and technology bring key advantages to the market. First, our products support the spectrum from 66 GHz to 71 GHz. These are often referred to as channels 5 and 6 in the 802.11ad/ay specifications. The key advantage in supporting these channels is that the signals are able to propagate much further than channels 1-4; this is a result of significantly lower oxygen absorption at frequencies above 66 GHz. Currently, customers have achieved links in the range of 25 kilometers, which we believe is substantially longer than any 60 GHz links achieved to date.

In the indoor area, the 802.11ad technology is ideal for high speed, low latency video applications. In indoor environments, our products can support 3 Gb/s links with under 5ms of latency. Example applications include:

•AR/VR links between the headset and the video console;

•Universal serial bus, or USB, video cameras for corporate video conferencing;

•Wireless security cameras; and

•Smart factory safety and surveillance.

We have developed a high-volume mmWave production test methodology using standard, low-cost production test equipment. It has taken us several years to refine performance of this production test methodology, and we believe this places us in a leadership position in addressing the operational challenges of competitively producing and delivering mmWave products into high-volume markets.

mmWave modules

In 2021, we began producing and selling complete mmWave modules. The primary advantage provided by a module is that the silicon and the antenna are integrated into a single device. A differentiating characteristic of mmWave technology is that the RF amplifiers must be as close as possible to the antenna to minimize loss. By providing a module, we can guarantee the performance of the amplifier to antenna interface, which simplifies the RF design engineering, facilitating more opportunities for companies that have not provided RF-type systems, as well as shortening the time to market for new products. It is possible for third parties to provide module products, but, given our significant mmWave antenna technology and intellectual property portfolio, we believe it enables us to provide a highly competitive solution, as we own the module technology and produce the significant module components.

Memory

Accelerator Engines

Our Accelerator Engine IC products are targeted for FPGA-based systems and include the Bandwidth Engine, which is targeted for high-performance applications where throughput is critical, and the Programmable HyperSpeed Engine, which combines the features of the Bandwidth Engine with 32 RISC processors to allow user-defined functions or algorithms to be embedded in the Programmable HyperSpeed Engine. The target applications for our memory ICs include a broad range of markets, including test and measurement, 5G networks, router, switching, security, computational storage, database acceleration, Big Data, aerospace and defense, advanced video, high-performance computing, machine learning and AI and other data-driven areas.

The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element. Our Bandwidth Engine ICs combine: (1) our proprietary high-density, high-speed, low latency embedded memory, (2) our high-speed serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM memory and serial interface with logic and other intelligence functions provides a system-level solution and significantly improves overall system performance at lower cost, size and power consumption. Our Bandwidth Engine ICs can provide up to and over 6.5 billion memory accesses per second externally and 12 billion memory accesses per second internally, which we believe is more than three times the performance of current memory-based solutions. They also can enable system designers to significantly narrow the gap between processor and memory IC performance. Our customers that design Bandwidth Engine ICs onto the line cards in their systems will re-architect their systems at the line-card level and use our product to replace traditional memory solutions. When compared with existing commercially available solutions, our Bandwidth Engine ICs may:

• provide up to four times the performance;

• reduce power consumption by approximately 50%;

• reduce cost by greater than 50%; and

• result in a dramatic reduction in IC pin counts on the line card.

Our Bandwidth Engine 2 IC products contain 576 megabits, or Mb, of memory and use a SerDes interface with up to 16 lanes operating at up to 12.5Gbps per lane. We have been shipping our Bandwidth Engine 2 IC products since 2013. Our Bandwidth Engine 3 IC products contain 1152Mb of memory and use a SerDes interface with up to 16 lanes operating at up to 25Gbps per lane. Our Bandwidth Engine 3 ICs target support for packet-processing applications with up to five billion memory single word accesses per second, as well as burst mode to enable full duplex buffering up to 400 Gbps for ingress, egress and oversubscription applications. The devices provide benefits of size, power, pin count and cost savings to our customers.

Our Programmable HyperSpeed Engine IC products further leverage our proven serial interface technology and high-density integrated memory with the processor engine architecture to enable high-speed customizable

search, security, and data analysis functions for networking, security, and data center applications, as well as new markets such as video and compute acceleration. The product architecture features 32 search-optimized processor engines, data flow schedulers, and over a terabit of internal access bandwidth. The device leverages our GCI interface technology and high-density integrated memory (1152Mb of 1T-SRAM embedded memory).

QPR

Our quad partition rate, or QPR, family of low cost, ultra-high speed SRAM memory devices features an architecture that allows for parallel accesses to multiple partitions of the memory simultaneously and allows access of up to 576 bits per read or write cycle. The QPR device includes four independent partitions per input/output and each partition functions as a stand-alone random-access SRAM. The high-performance interface, larger density and the multiple partitions work together to support multiple independent functional blocks within an FPGA with one QPR device. The MoSys MSQ220 and MSQ230 QPR devices are ideally suited for random-access applications. We also offer an optional FPGA RTL memory controller to simplify the interface to its high capacity 567Mb or 1Gb devices. We also offer an RTL memory controller that presents an SRAM-like interface to simplify the QPR design effort.

Research and Development

Our ability to compete in the future depends on successfully improving our technology to meet the market’s increasing demand for higher performance and lower cost solutions. Development of new IC products requires specialized chip design and product engineers, as well as significant fabrication and testing costs, including mask costs.

We have over 12 years’ worth of technical know-how in the design and manufacturing of mmWave technology. The most important aspect of this knowledge is knowing how mmWave circuits will perform in a real-world environment. Traditionally, semiconductor design utilizes sophisticated computer-aided design tools to simulate the performance of a device that is manufactured at a specific semiconductor manufacturing plant. However, mmWave is extremely difficult to model precisely. Therefore, the only path to understand how well a device will perform is to produce the device and test it in a real-world application. Over the last decade, many companies have attempted to develop mmWave semiconductor devices, however, given that the devices had inconsistent or weak performance, a number of them were unsuccessful and abandoned their design and product development efforts.

At a system level, there are additional technical challenges presented by mmWave technology that Peraso has overcome and form a key part of the internal know-how of Peraso. For example, a key technology of mmWave is the concept of beamforming and beam steering using a phased array antenna. This technology is utilized to concentrate the RF energy into a narrow beam to improve the range and coverage of mmWave devices. We have developed effective of beamforming and beam steering technology for phased array circuits and antennas. While there are many academic examples of successful phased array implementations, there is a vast barrier between a “laboratory” version of phased array technology and a version that is deployed for commercial use. One such aspect is the implementation of the beamforming procedure, which seeks to maximize throughput and do so while not impacting latency. While the details of achieving this are complex, it is important-intellectual property that we have gained through real-world experience.

With regard to our memory products, we do not have internal resources to develop new, memory IC products, and do not intend to expend any development efforts to develop new memory products. That said, we believe our Accelerator Engine IC products will provide us with meaningful revenue and gross margin contributions for the foreseeable future. We intend to continue to devote substantially all of our research and development efforts toward further expanding our mmWave technology portfolio.

Sales and Marketing

In addition to our direct sales personnel, we sell through sales representatives and distributors in the United States and Asia. During 2020, we entered into new distribution relationships with Arrow Electronics and DigiKey Electronics, which are two of the largest worldwide IC distributors. These distributors have a global presence with offices and technical selling and applications engineering capabilities, which we believe will enable us to reach new potential customers for our products.

We also have applications engineers who support our customer engagements and engage with the customers’ system architects and designers to propose and implement our IC and IP solutions to address system design challenges and improve performance.

In the markets we serve, the time from a design win to production volume shipments of our IC products can range from 12 to 36 months. Networking, wireless and wired communication and security appliance systems can have a product life from a few years to over 10 years once a product like ours has been designed into the system. Historically, our revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue.

During the year ended December 31, 2021, three customers accounted for 10% or more of our net revenues, including CEAC International Limited at 48%, WeLink Communications LLC at 19% and Alltek Technology Corp at 12%. During the year ended December 31, 2020, three customers accounted for 10% or more of our net revenues, including Ubiquiti Inc. at 55%, XCOM Labs, Inc. at 27% and Alltek Technology Corp at 12%.

Intellectual Property

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of December 31, 2021, we held 105 United States and 55 foreign patents on various aspects of our mmWave, antenna, memory and other technology, with expiration dates ranging from 2022 to 2040. We also held 25 pending patent applications in the United States and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

We were also an active participant in the development of the IEEE 802.11ay wireless specification and, to date, have been granted nine essential claims patents with respect to this standard. Essential claims patents are of particular value as a specification cannot be implemented without violating the patents.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our IC customers, licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, “Risk Factors.”

Competition

mmWave

mmWave circuit and system design is a highly specialized engineering skill, as well as a challenging technology to ship in mass production. At frequencies above 24 GHz, circuits are extremely vulnerable to small variances in the semiconductor manufacturing process. Designing circuits that minimize susceptibility to these variances takes years of practice, and we believe we are one of the few companies in the world that is skilled in mmWave design. Further, we have shipped mmWave devices in volume, and ensuring all devices sold adhere to strict performance standards is a core competency we have developed. In addition, we have developed our own mmWave phased array antenna technology, which allows us to be highly competitive in terms of overall system cost. Our customers do not need to engage with third-party antenna suppliers, thus eliminating the additional cost for a third-party antenna.

IEEE 802.11ad/ay Market:

Our primary competitor in the IEEE802.11ad/ay market is Qualcomm. The primary benefit that we provide to the market is the support of the higher frequency bands from 66 GHz to 71 GHz. The advantage at these frequencies is that oxygen attenuation is significantly reduced, and signals can travel much further.

We also have key points of differentiation compared to Qualcomm for wireless video devices. We are well positioned in this market, as we have USB 3.0 built into our devices, so our products generally support USB architectures. A prime example is the replacement of the USB cable with a wireless version using our technology. There are many applications where this can be of use, including USB web cams, wireless displays, and AR/VR headsets. We have invested significant software resources into providing the market with wireless USB solutions, and we believe there is no other mmWave vendor in the world that can offer multi-gigabit solutions as a replacement for wired USB.

5G Market:

With 5G, our efforts are focused on the mmWave RF front-end phased array component of the system. This focus is in contrast to the IEEE solution, in which Peraso provides a baseband device as well as an mmWave RF front-end phased array device. The 5G product instantiation is an RF module that embraces a broad swath of intellectual property that establishes a substantial moat to potential competitors. Key elements of our mmWave intellectual property include:

•RF circuits;

•phased array antenna; and

•in-system circuit calibration, beam forming, real-time system monitoring.

From a competitive perspective, we are currently the only pure-play, 5G vendor to offer a dual-band (28/39GHz) RF solution for the FWA market. Qualcomm does offer a 5G RF solution for the FWA market, however its solution is based on aggregating its mobile RF solution, which requires several compromises in terms of cost, performance, and power consumption. With an initial focus on fixed wireless access, we can derive advantages by optimizing our silicon for that specific market. Furthermore, we have experienced initial success in the unlicensed, 60 GHz, FWA market, and we believe we will be able to transfer all of our knowledge gained from the 60 GHz market to the 5G market. However, this market opportunity is more competitive, and potential competitors, in addition to Qualcomm, include Mediatek and Samsung Electronics Co., Ltd., or Samsung.

Memory

The markets for our memory products are highly competitive. We believe that the principal competitive factors are:

• processing speed and performance;

• density and cost;

• power consumption;

• reliability;

• interface requirements;

• ease with which technology can be customized for and incorporated into customers’ products; and

• level of technical support provided.

We believe that our products compete favorably with respect to each of these criteria. Our proprietary 1T-SRAM embedded memory and high-speed serial interface IP can provide our Accelerator Engine ICs with a competitive advantage over alternative devices. Alternative solutions are either DRAM or SRAM-based and can support either the memory size or speed requirements of high-performance networking systems, but generally not both. DRAM solutions provide a significant amount of memory at competitive cost, but DRAM solutions do not have the required fast access and cycle times to enable high-performance. The DRAM solutions currently used in networking systems include RLDRAM from Micron Technology, Inc., or Micron, LLDRAM from Renesas, DDR from Samsung, Micron and others, and HBM, which is stacked DRAM memory from Samsung and SK Hynix. SRAM solutions can meet high-speed performance requirements, but often lack adequate memory size. The SRAM solutions currently used in networking systems primarily include QDR or similar SRAM products from Cypress Semiconductor Corporation and GSI Technology, Inc. Most of the currently available SRAM and DRAM solutions use a parallel, rather than a serial interface. To offset these drawbacks, system designers generally must use more discrete memory ICs, resulting in higher power consumption and greater utilization of space on the line card.

Our competitors include established semiconductor companies with significantly longer operating histories, greater name recognition and reputation, large customer bases, dedicated manufacturing facilities and greater financial, technical, sales and marketing resources. This may allow them to respond more quickly than us to new or emerging technologies or changes in customer requirements. Generally, customers prefer suppliers with greater financial resources than we have currently. Many of our competitors also have significant influence in the semiconductor industry. They may be able to introduce new technologies or devote greater resources to the development, marketing and sales of their products than we can. Furthermore, in the event of a manufacturing capacity shortage, these competitors may be able to manufacture products when we are unable to do so.

Our Accelerator Engine ICs compete with embedded memory solutions, stand-alone memory ICs, including both DRAM and SRAM ICs, ASICs designed by customers in-house to meet their system requirements, and NPUs that use significant internal memory and customer-designed software to implement tasks.

Manufacturing

We depend on third-party vendors to manufacture, package, assemble and test our IC products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility. By outsourcing manufacturing, we can avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

We perform an ongoing review of our product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meets design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers.

Employees

As of December 31, 2021, we had 82 employees, including 22 located in the United States and 60 located in Canada. Our headcount consists of 64 in research and development and manufacturing operations and 18 in sales, marketing and general and administrative functions.

Available Information

We were founded in 1991 and reincorporated in Delaware in 2000. Our website address is www.peraso.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Exchange Act, as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read any materials submitted electronically by us to the SEC on its website (www.sec.gov), which contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Overview

MoSys, Inc., together with its subsidiaries (“MoSys,” the “Company,” “we,” “our” or “us”), is a fabless semiconductor company focused on the development and sale of integrated circuits, or ICs, for the high-speed cloud networking, communications, security appliance, video, monitor and test, data center and computing markets. Our solutions deliver time-to-market, performance, power, area and economic benefits for system original equipment manufacturers, or OEMs. Our primary product line is marketed under the Accelerator Engine name and comprises our Bandwidth Engine and Programmable HyperSpeed Engine IC products, which integrate our proprietary, 1T-SRAM high-density embedded memory and a highly-efficient serial interface protocol resulting in a monolithic memory IC solution optimized for memory bandwidth and transaction access performance. Further performance benefits can be achieved to offload statistical, search or other custom functions using our optional integrated logic and processor elements.

As data rates and the amount of high-speed processing increase, critical memory access bottlenecks occur. Our Accelerator Engine ICs dramatically increase memory accesses per second, removing these bottlenecks. In addition, the serial interface and high-memory capacity reduce the board footprint, number of pins and complexity, while using less power. To complement our Accelerator Engine ICs and utilize our technology we have been developing our Virtual Accelerator Engine, or VAE, product line that leverages our proprietary graph memory engine technology to provide data classification capabilities through the use of high-speed memories. Our VAE products include software, firmware and related intellectual property, or IP, and are hardware agnostic and operate with or without one of our Accelerator Engine IC products.

Our LineSpeed IC product line comprises non-memory, high-speed serialization-deserialization interface, or SerDes I/O, physical layer, or PHY, devices that ensure signal integrity between interfaces which is commonly referred to as clock data recovery, or CDR, or retimer functionality, which perform multiplexing to transition from one speed to another, commonly referred to as Gearbox functionality. These PHY devices reside within optical modules and on networking equipment line cards designed for next-generation Ethernet and optical transport network applications.

Industry Background

The amount of data and the number of data consumers and devices continues to grow, driven primarily by commercial and consumer cloud applications, video services, high speed mobile networks, Internet of Things, or IoT, and many other cloud applications. In order to meet these demands, the new cloud infrastructure, including the backbone, edge, access network and data centers, must scale in both speed and intelligence to handle real-time security, bandwidth allocation, and service-level expectations. In addition, workloads or applications delivered at a massive scale from the cloud require flexible and efficient data transmission to optimize resources to enable these applications and lower the overall cost, size and power of the data center. These increased demands strain communication between onboard IC devices, limiting the data throughput in network switches and routers and the network backbone.

To meet these demands, carrier and enterprise networks are merging with the cloud and are undergoing significant changes and, most significantly, are migrating to packet-based Ethernet networks that enable higher throughput, lower cost and uniform technology across access, core and metro network infrastructure. These networks have been designed to deliver voice and video applications over high-speed Internet services on one converged, efficient and flexible network. These trends require networking systems, especially the high-speed switches, security appliances and routers that primarily comprise these networks, to comply with evolving market requirements and be capable of providing new services and better quality of service while supporting new protocols and standards. Traditional OEM network and telecommunications equipment manufacturers, such as Nokia Corporation, and its subsidiary, Alcatel-Lucent, Cisco Systems, Inc., Tel. LM Ericsson, Fujitsu Ltd., Hitachi Ltd., Huawei Technologies, and Juniper Networks, Inc., as well as new vendors and cloud-service providers, who are delivering a new set of white-box solutions, must offer higher levels of packet forwarding rates, bandwidth density and be optimized to enable higher-density, lower-power data path connectivity in the next generations of their networking systems.

Networking communications, security, video and computing systems throughout the cloud network must operate at higher speed and performance levels, and so require new generations of packet processors and improved memory subsystems to enable system performance. These systems and their component line cards generally need to support aggregate rates of 100 gigabits per second, or Gbps, and above to meet the continued growth in network traffic. Data centers and access equipment that were previously aggregating slower traffic at rates of up to 40Gbps now are being designed to aggregate traffic at 100Gbps, or more. The transition to high-bandwidth networks and the move to 100Gbps and higher rates at the edge (i.e., closer to the networks and users generating data, voice and video traffic) is underway, and the increase in data rates for these networks is expected to continue to grow rapidly over the coming years.

The systems that our customers build come in various sizes and utilize cards that contain several types of semiconductors. Line cards are found in chassis-based systems that have slots and can contain up to 20 line cards. Our networking and communication system and certain other system customers typically use chassis-based systems. The alternative is systems that contain a single card; these systems are generally referred to as appliances or “pizza boxes.” Cards that typically plug into a server or compute system are generally referred to as accelerator cards. We believe the wider use of these accelerator cards in systems throughout the network, especially at the edge, will expand the market opportunity for our products, as a number of these cards utilize field programmable gate array ICs, or FPGAs, as the packet processor. Our Accelerator Engines are ideally suited to support FPGAs performing these functions. Each line card, or accelerator card, includes one or more processors and multiple memory chips. These processors are complex ICs or IC chipsets that perform high-speed data or packet processing for functions, such as traffic routing, shaping, metering, billing, statistics, detection, steering, security, video processing, monitoring and workload acceleration. The line cards use various types of memory ICs to facilitate temporary packet storage and assist in the analysis and tracking of information embedded within the data flowing through the processors. After a packet enters the line card, a packet or data processor helps separate the packet into smaller pieces for rapid analysis. In a typical packet-based network for example, the data is broken up into the packet

header, which contains vital information on packet destination and type, such as the Internet protocol address, and the payload, which contains the data being sent. Generally, the line card operations must occur at full data rates and typically require frequent access to the memory ICs.

Simultaneously, the packet’s payload, which may be substantially larger than the packet header, is also stored in memory ICs until processing is complete and the packet can be re-combined and sent to its next system destination. Within the line card, communication between the packet processor and memory ICs occurs through an interface consisting of combinations of physical pins on each type of chip. These pins are grouped together in a parallel or a serial architecture to form a pathway, called a bus, through which information is transferred from one IC to the next.

Today, the majority of physical buses that connect networking equipment and components use a parallel architecture to communicate between processors and memory ICs, which means information can travel only in one direction and in one instance at a time. As processing speeds increase, the number of pins required and the speed of the bus in a parallel architecture become a limitation on system performance and capability. In contrast, the number of connections is reduced substantially across fewer, higher-rate pins in a serial architecture, and data is transferred simultaneously in both directions. Data transfer rates are limited by the data access rates of the various ICs included on the line card, thus leading to bottlenecks when these ICs perform inadequately. In order to remove these bottlenecks and meet next-generation bandwidth requirements, the line card ICs need to support higher access rates enabled by internal memory or high-speed serial bus architectures and these more advanced interface protocols.

Most networking and communication systems sold and in operation today include line cards that process data at speeds ranging from 10Gbps to 400Gbps, and support many aggregated slower ports. To accommodate the substantial and growing increase in demand for networking communications and applications, networking systems manufacturers are developing and bringing to market next-generation systems that run at aggregate speeds of 400 Gbps or more with newer products scaling to tens of thousands of Gbps, or tens of terabits, per second. Applications, such as security appliances, broadcast video and compute accelerators that were previously running at aggregate rates of 10Gbps or 40Gbps, are moving to higher aggregate rates in the 100s of Gbps. Although processor performance in applications, such as computing and networking has traditionally doubled nearly every 18 months, or even sooner, the performance of external high-density memory technology has generally been able to double only once every 10 years. Existing memory IC solutions built for high capacity and based on parallel interface architecture struggle to meet the access rates required to meet speeds of 100Gbps and beyond due to system-level limitations for pin counts, power and performance. To compensate for slow external memory access, developers must either integrate larger amounts of on-chip memory and/or utilize complex system alternatives to try to work around the access-rate limitations of these memories. The additional memory and circuitry adds to IC power, size and cost and may not be feasible depending on the economics and technology used to implement the data processor. These networking and communications systems generally comprise a chassis populated by 4 to 16 line cards. Often, these systems are shipped to customers with only a portion of the line card slots populated, and the customer will add additional line cards to increase system performance, capacity and features.

Each line card requires a significant amount of memory to support its processing capabilities. Traditional external memory IC solutions currently used on line cards include both dynamic random access memory, or DRAM, and static random access memory, or SRAM. Line cards in networking systems use both specialized, high-performance DRAM ICs, such as reduced-latency DRAM, or RLDRAM, low-latency DRAM, or LLDRAM, and commodity DRAM, such as double data rate, or DDR ICs. The latest DDR memory is high-bandwidth memory, or HBM, which provides high bandwidth, but has fundamentally slow access time. For very high access, networking systems use higher-performance SRAM, which may be integrated into the data processing IC itself depending on size, power and economics or use a traditional external SRAM IC, such as quad data rate, or QDR SRAM. These memories are very fast, but are much smaller, cost more and burn more power than traditional DRAM. Substantially all of these traditional memory IC solutions use parallel interfaces, which are slower than serial interfaces. For data processing solutions, which are unable to integrate sufficient amounts of SRAM, such as FPGAs, we believe the external SRAMs or RLDRAMs will be increasingly challenged to meet the performance, pin count, area and power requirements as networking systems and other new security, video, and compute systems expand beyond 400Gbps. The result is a gap between processor and memory performance. To meet the higher performance requirements being demanded by the industry, while using current components and architectural approaches, system designers must add more discrete memory ICs to the line cards and/or add more embedded memory on the packet processor. New processor and custom data processing engine ICs are being developed that integrate more SRAM to help offset the bottlenecks, but the cost to develop these custom ICs is high and there is a trade-off in cost, power and size.

FPGAs offer flexibility, lower development cost and time to market but are limited in the amount of internal circuitry and the amount of integrated SRAM memory. We believe our Accelerator Engine family of products is well suited to address memory access bottleneck challenges and provide significant performance, size, pin count and power advantages compared to traditional external memory solutions, primarily for FPGA-based systems.

In order to improve performance and resolve memory bottlenecks, in recent years, the trend has been to have algorithms on the memory device perform computations in order to reduce processing time and power consumption. This trend is sometimes called in-memory compute or processor-in-memory. In order to make a flexible solution, the in-memory compute can be accomplished with arrays of reduced instruction set computer, or RISC, cores on the memory device. Further performance gains can be accomplished with application-specific enhancements to the memory device’s instruction set architecture.

We have developed our ICs to synergistically address the need for high-speed data access and throughput currently confronting system designers. We expect our IC products to meet the increasing demands placed on conventional memory technology used on the line cards in high-speed systems. We believe that our products and technology are well positioned as replacements for existing IC solutions in order to support the needs of a growing number of FPGA-based data processing applications with aggregate rates greater than 100Gbps that require high bandwidth and high access rate to memory.

Our Approach

We have leveraged our proprietary IP to design our IC products and related acceleration IP to help OEMs in our target markets to address the growing bottlenecks in system performance. We have incorporated critical features into our product families to accomplish this objective.

High-Performance Interface

High-speed, efficient interfaces are critical building blocks to meet high data transfer rate requirements for communication between ICs on network line cards. Semiconductor companies are increasingly turning to serial interface architectures to achieve needed system performance. Using serial interfaces, IC developers also are able to reduce the number of pins (the wired electrical pins that connect an IC to the network line card on which it is mounted) on the IC. With reducing geometries, the size of most high-performance ICs is dictated by the number of pins required, rather than the amount of logic and memory embedded in the chip. As a result, using a serial interface facilitates cost reduction and reduced system power consumption, while improving the performance of both the IC itself and the overall system. While serial interfaces provide significantly enhanced performance over parallel interfaces, SerDes interfaces traditionally have had higher power consumption, which is a challenge for IC designers. Our SerDes interfaces, however, are optimized to meet our customers’ signal integrity, low-power consumption and latency requirements.

We make our interface technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering development and validation costs.

GigaChip Interface Protocol

In addition to the physical characteristics of the serial interface, the protocol used to transmit data is also an important element that impacts speed and performance. To address this and complement our Accelerator Engine devices, we have developed the GigaChip Interface, or GCI, which is an open-interface transport protocol optimized for efficient chip-to-chip communications. The GCI electrical interface is compatible with the current industry standards, including 10G and 25G IEEE and OIF interface standards, to simplify electrical interoperability between devices. GCI can enable highly efficient serial chip-to-chip communications, and its transport efficiency averages 90% for the data transfers it handles. GCI is included in our ICs and is offered to customers and prospective partners on terms intended to encourage widespread adoption.

High-Performance and High-Density Memory Architecture

The high density of our proprietary 1T-SRAM technology stems from the use of a single-transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM. Embedded memory utilizing our 1T-SRAM technologies typically provides speeds essentially equal to or greater than the speeds of traditional SRAM and DRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than DRAM technology. Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generate less heat than traditional SRAM when operating at the same speed. The 1T-SRAM allows us to integrate more high-performance memory using less expensive processing technology, reduce system level heat dissipation and enable reliable operation using lower-cost packaging.

Embedded In-Memory Functions

We have combined our high-speed memory architecture with intelligence to define an embedded memory that can execute embedded functions and algorithms internally, or “in-memory,” to allow software and hardware designers acceleration options to improve the performance of their applications.

The in-memory functions executed within the memory architecture in our Accelerator Engine IC products result in application-performance increases by reducing the number of external memory and computational operations needed to accomplish the same functions using traditional memories. Also, by executing in-memory, the resources of the packet processor and other ICs on a customer board are available to perform other functions.

Our Accelerator Engine ICs include an arithmetic logic unit, or ALU, which enables the performance of mathematical operations on data. Moving certain processing functions from the host data processor IC to the Accelerator Engine IC through the use of this embedded ALU, reduces the number of processing transactions and frees the host data processor IC to perform other important networking or micro-processing functions.

Our Programmable HyperSpeed Engine IC takes this concept one step further by incorporating integrated RISC processors optimized for processing data structures and graphs. Our Programmable HyperSpeed Engine IC integrates RISC cores optimized for operating data stored in the memory block. The integration of the cores with memory allows system algorithms or functions to be offloaded to the device and reduces overall system-task latency and increases throughput. The processors can be programmed by the user to offload and accelerate standard and/or customized functions from the main processor thereby reducing memory transactions and data path complexity to provide improved performance and lower system latency. New algorithms or functions can be added to or modified in the Programmable HyperSpeed Engine IC in software.

Our Strategy

Our primary business objective is to be a profitable IP-rich fabless semiconductor company offering ICs and related software and IP that deliver unparalleled memory bandwidth and access rate performance for high-performance data processing in cloud networking, security appliances, video, test and monitoring, and data center systems. The key components of our strategic plan include the following strategies:

Target Large and Growing Markets

Prior to 2019, our primary focus was the multi-billion dollar networking, telecommunications, security appliance and data center OEM equipment markets, as our products were developed to support the growth in 100Gbps and higher networking speeds. During 2019, we expanded our market focus to new markets, including video, test and measurement and computing markets. We are currently supporting customers across these markets, with whom we have achieved design wins. We define a design win as a commitment from a customer to utilize one of our IC products in its system. We continue to actively pursue additional design wins for the use of our ICs in our target markets. We believe our design wins represent the potential for future revenue growth. However, there is no assurance that these customer designs will be shipped in large volume by our customers to their customers, how much revenue each design win is likely to generate, or how much revenue all of these (and future design wins) are likely to generate.

Build Long-Term Relationships with FPGA Vendors and Suppliers of Data Processing Solutions

We believe that having long-term relationships with FPGA providers is critical to our success, as such relationships enable us to reduce our time-to-market, provide us with a competitive advantage, identify additional IC design win and licensing opportunities and expand our target markets. A key consideration of network system designers is to demonstrate interoperability between our IC products and the processor ICs utilized in their systems. To obtain design wins, we must demonstrate this interoperability, and also show that our IC products work optimally with the packet processor to achieve the performance requirements. In addition, our current strategy requires packet processor suppliers to adopt our GCI interface. To that end, we have been working closely with FPGA and application specific standard product providers to enable interoperability between our Accelerator Engine IC products and their high-performance products. To facilitate the acceptance of our Accelerator Engine ICs, we have made available development and characterization kits for system designers to evaluate and develop code for next-generation networking systems. Our characterization kits are fully-functional hardware platforms that allow FPGA and ASIC providers, and their customers, to demonstrate interoperability of the Accelerator Engine IC with the ASIC or FPGA the designers use within their systems.

Our IC Products

Accelerator Engines

Our Accelerator Engine IC products, include the Bandwidth Engine, which is targeted for high-performance applications where throughput is critical, and the Programmable HyperSpeed Engine, which combines the features of the Bandwidth Engine with 32 RISC processors to allow user-defined functions or algorithms to be embedded in the Programmable HyperSpeed Engine.

Bandwidth Engine

The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element. Our Bandwidth Engine ICs combine: (1) our proprietary high-density, high-speed, low latency embedded memory, (2) our high-speed serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM memory and serial interface with logic and other intelligence functions provides a system-level solution and significantly improves overall system performance at lower cost, size and power consumption. Our Bandwidth Engine ICs can provide up to and over 6.5 billion memory accesses per second externally and 12 billion memory accesses per second internally, which we believe is more than three times the performance of current memory-based solutions. They also can enable system designers to significantly narrow the gap between processor and memory IC performance. Our customers that design Bandwidth Engine ICs onto the line cards in their systems will re-architect their systems at the line-card level and use our product to replace traditional memory solutions. When compared with existing commercially available solutions, our Bandwidth Engine ICs may:

• provide up to four times the performance;

• reduce power consumption by approximately 50%;

• reduce cost by greater than 50%; and

• result in a dramatic reduction in IC pin counts on the line card.

Our Bandwidth Engine 2 IC products contain 576 megabits, or Mb, of memory and use a SerDes interface with up to 16 lanes operating at up to 12.5Gbps per lane. We have been shipping our Bandwidth Engine 2 IC products since 2013. We continue to win new designs for this device family, and expect these products to be our primary revenue source for the foreseeable future.

Our Bandwidth Engine 3 IC products contain 1152Mb of memory and use a SerDes interface with up to 16 lanes operating at up to 25Gbps per lane. Our Bandwidth Engine 3 ICs target support for packet-processing applications with up to five billion memory single word accesses per second, as well as burst mode to enable full duplex buffering up to 400 Gbps for ingress, egress and oversubscription applications. The devices provide benefits of size, power, pin count and cost savings to our customers.

Programmable HyperSpeed Engine

Our Programmable HyperSpeed Engine IC products further leverage our proven serial interface technology and high-density integrated memory with the processor engine architecture to enable high-speed customizable search, security, and data analysis functions for networking, security, and data center applications, as well as new markets such as video and compute acceleration. The product architecture features 32 search-optimized processor engines, data flow schedulers, and over a terabit of internal access bandwidth. The device leverages our GCI interface technology and high-density integrated memory (1152Mb of 1T-SRAM embedded memory).

QPR

During 2020, we launched a new line of memory ICs, our quad partition rate, or QPR, family of low cost, ultra-high speed SRAM memory devices optimized for FPGA-based systems.

Our QPR memory technology features an architecture that allows for parallel accesses to multiple partitions of the memory simultaneously and allows access of up to 576 bits per read or write cycle. The QPR device includes four independent partitions per input/output and each partition functions as a stand-alone random-access SRAM. The high-performance interface, larger density and the multiple partitions work together to support multiple independent functional blocks within an FPGA with one QPR device. The MoSys MSQ220 and MSQ230 QPR devices are ideally suited for random-access applications. MoSys also offers an optional FPGA RTL memory controller to simplify the interface to its high capacity 567Mb or 1Gb devices. We also offer an RTL memory controller that presents an SRAM-like interface to simplify the QPR design effort.

The target applications are FPGA-based and include a broad range of markets, including test and measurement, 5G networks, router, switching, security, computational storage, database acceleration, Big Data, aerospace and defense, advanced video, high-performance computing, machine learning and AI and other data-driven areas.

LineSpeed Flex PHYs

Our LineSpeed Flex family of 100G PHYs, is designed to support industry standards and includes gearbox, Multi-Link Gearbox, or MLG, and high density CDR/retimer devices designed to enable Ethernet and OTN line card applications to support the latest electrical and optical interfaces.

IP Licensing

1T-SRAM

Historically, we licensed our IT-SRAM memory and SerDes interface technologies on a worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies. Most of these licensees incorporated our technology into ICs that they sold to their customers, and, in the case of IT-SRAM licenses, pay a royalty to us for each IC shipped that incorporates our technology. Royalty and other revenue generated from our legacy IP agreements represented 12% and 7% of our total revenues for 2020 and 2019, respectively.

Virtual Accelerator Engines

Recently, we announced our new VAE product line that consists of software, firmware and other IP, such as register-transfer level, or RTL, code and utilizes a common application programming interface and common RTL interface to facilitate platform portability. This new product line will include multiple function accelerator platform products, which target specific application functions and will use a common software interface to allow performance scalability over multiple hardware environments. These function accelerator platform products are hardware agnostic and operate with or without one of our Accelerator Engine ICs. For example, our VAE IP can run on a processing unit IC or FPGA that is not attached to a MoSys IC or an FPGA that is attached to a MoSys IC, such as the Bandwidth Engine or Programmable HyperSpeed Engine.

Our initial VAE product is our graph memory engine, or GME, accelerator IP, which is part of our packet classification platform, for performing embedded search and classification of packet headers. A typical use would be an alternative to ternary content-addressable memory, or TCAM, which is a specialized type of high-speed memory that searches its entire contents in a single clock cycle. While TCAMs enable the highest levels of performance, they are monolithic ICs that are limited in capacity and consume large amounts of power. In comparison, our GME IP can be integrated into the existing processor chip or chipset with no additional stand-alone IC required. Our

proprietary platform software enables the compilation of TCAM images into graphs for GME processing utilizing a wider range of memory types including DRAM.

We believe the technology will generate new opportunities that require less up-front architectural changes by system designers and provide a scalable capacity and performance roadmap of options using our Accelerator Engine ICs. We began pursuing license opportunities for our VAE products in 2020 and expect to begin achieving production licenses for these products in 2021.

Research and Development

Our ability to compete in the future depends on successfully improving our technology to meet the market’s increasing demand for higher performance and lower cost solutions. Development of new IC products requires specialized chip design and product engineers, as well as significant fabrication and testing costs, including mask costs. We currently do not have internal resources for new IC products. That said, we believe our Accelerator Engine IC product portfolio will provide us with adequate revenue growth opportunity for the foreseeable future. We have focused our product development efforts on software-based capabilities and features that leverage our current technologies and core competencies and complement, our Accelerator Engine IC products. As discussed above, we recently announced our VAE product line, and the initial packet classification products will use our graph memory engine for performing embedded search and classification of packet headers. We intend to continue to devote the majority of our research and development efforts toward furthering our VAE product roadmap and, where applicable, developing customer-specific IP.

Sales and Marketing

We believe that systems OEMs typically prefer to extend the use of traditional memory solutions and their parallel interfaces, despite performance and costs challenges, and are reluctant to change their technology platforms and adopt new designs and technologies, such as serial interfaces, which are an integral part of our product solutions. Therefore, our principal selling and marketing activities to date have been focused on persuading these OEMs and key component specialists that our IC products provide critical performance advantages, as well as on securing design wins with them.

In addition to our direct sales personnel, we sell through sales representatives and distributors in the United States and Asia. During 2020, we entered into new distribution relationships with Arrow Electronics and DigiKey Electronics, which are two of the largest worldwide IC distributors. These distributors have a global presence with offices and technical selling and applications, which we believe will enable us to reach new potential customers for our products.

We also have applications engineers who support our customer engagements and engage with the customers’ system architects and designers to propose and implement our IC and IP solutions to address system design challenges and improve performance.

In the markets we serve, the time from a design win to production volume shipments of our IC products can range from 18 to 36 months. Networking, communications and security appliance systems can have a product life from a few years to over 10 years once a product like ours has been designed into the system. Our revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue.

The following customers accounted for 10% or more of our net revenues in one or more of the following periods:

Year Ended December 31, 2020 2019 Flextronics 37% 30% Sanmina 22% 14% Clavis 10% 17% Nokia/ALU 10% * Palo Alto Networks * 13%

*Represents less than 10%

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of December 31, 2020, we held 66 U.S. and 33 foreign patents on various aspects of our technology, with expiration dates ranging from 2022 to 2037. We also held 4 pending patent applications in the U.S. and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our IC customers, licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, “Risk Factors.”

Competition

The markets for our products are highly competitive. We believe that the principal competitive factors are:

• processing speed and performance;

• density and cost;

• power consumption;

• reliability;

• interface requirements;

• ease with which technology can be customized for and incorporated into customers’ products; and

• level of technical support provided.

We believe that our products compete favorably with respect to each of these criteria. Our proprietary 1T-SRAM embedded memory and high-speed serial interface IP can provide our Accelerator Engine ICs with a competitive advantage over alternative devices. Alternative solutions are either DRAM or SRAM-based and can support either the memory size or speed requirements of high-performance networking systems, but generally not both. DRAM solutions provide a significant amount of memory at competitive cost, but DRAM solutions do not have the required fast access and cycle times to enable high-performance. The DRAM solutions currently used in networking systems include RLDRAM from Micron Technology, Inc., or Micron, LLDRAM from Renesas, DDR from Samsung Electronics Co., Ltd., Micron and others, and HBM, which is stacked DRAM memory from Samsung Electronics Co. and SK Hynix. SRAM solutions can meet high-speed performance requirements, but often lack adequate memory size. The SRAM solutions currently used in networking systems primarily include QDR or similar SRAM products from Cypress Semiconductor Corporation and GSI Technology, Inc. Most of the currently available SRAM and DRAM solutions use a parallel, rather than a serial interface. To offset these drawbacks, system designers generally must use more discrete memory ICs, resulting in higher power consumption and greater utilization of space on the line card.

Our competitors include established semiconductor companies with significantly longer operating histories, greater name recognition and reputation, large customer bases, dedicated manufacturing facilities and greater financial, technical, sales and marketing resources. This may allow them to respond more quickly than us to new or emerging technologies or changes in customer requirements. Generally, customers prefer suppliers with greater financial resources than we have currently. Many of our competitors also have significant influence in the semiconductor industry. They may be able to introduce new technologies or devote greater resources to the development, marketing and sales of their products than we can. Furthermore, in the event of a manufacturing capacity shortage, these competitors may be able to manufacture products when we are unable to do so.

Our Accelerator Engine ICs compete with embedded memory solutions, stand-alone memory ICs, including both DRAM and SRAM ICs, ASICs designed by customers in-house to meet their system requirements, and NPUs that use significant internal memory and customer-designed software to implement tasks. Our prospective customers may be unwilling to adopt and design-in our ICs due to the uncertainties and risks surrounding designing a new IC into their systems and relying on a supplier that has limited history of manufacturing such ICs and limited financial resources. In addition, our Accelerator Engine ICs require the customer and its other IC suppliers to implement our chip-to-chip communication protocol, the GCI interface. These parties may be unwilling to do this if they believe it could adversely impact their own future product developments or competitive advantages, or, if they believe it might complicate their development process or increase the cost of their products. To remain competitive, we believe we must provide unparalleled memory IC solutions with the highest bandwidth capability for our target markets, which solutions are engineered and built for high-reliability carrier and enterprise applications.

Our LineSpeed PHY ICs compete with solutions offered by Broadcom Ltd., Inphi Corporation, M/A-COM Technology Solutions Holdings, Inc. and Semtech Corp., as well as other smaller analog signal processing companies. We also may compete with ASICs designed by customers in-house to meet their system requirements, as well as by optical module OEMs. The market for our LineSpeed products is highly competitive, and customers have a number of suppliers they can choose from. We must provide differentiated features with a reasonable IC power budget, while offering competitive pricing. To date, we have had limited success selling and marketing these products.

Manufacturing

We depend on third-party vendors to manufacture, package, assemble and test our IC products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility. By outsourcing manufacturing, we can avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

We perform an ongoing review of our product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meets design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers. We have achieved ISO 9001:2015 certification, and all of our significant manufacturing vendors have also achieved ISO 9001 certification.

Employees

As of December 31, 2020, we had 24 employees all of whom are located in the United States, consisting of 15 in research and development and manufacturing operations and 9 in sales, marketing and general and administrative functions.

Available Information

We were founded in 1991 and reincorporated in Delaware in 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Exchange Act, as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read any materials submitted electronically by us to the SEC on its website (www.sec.gov), which contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Overview

MoSys, Inc., together with its subsidiaries (“MoSys,” the “Company,” “we,” “our” or “us”), is a fabless semiconductor company focused on the development and sale of integrated circuits, or ICs, for the high-speed cloud networking, communications, security appliance, video, monitor and test, data center and computing markets. Our solutions deliver time-to-market, performance, power, area and economic benefits for system original equipment manufacturers, or OEMs. Our primary product line is marketed under the Accelerator Engine name and comprises our Bandwidth Engine and Programmable HyperSpeed Engine IC products, which integrate our proprietary, 1T-SRAM high-density embedded memory and a highly-efficient serial interface protocol resulting in a monolithic memory IC solution optimized for memory bandwidth and transaction access performance. Further performance benefits can be achieved to offload statistical, search or other custom functions using our optional integrated logic and processor elements.

As data rates and the amount of high-speed processing increase, critical memory access bottlenecks occur. Our Accelerator Engine ICs dramatically increase memory accesses per second, removing these bottlenecks. In addition, the serial interface and high-memory capacity reduce the board footprint, number of pins and complexity, while using less power. To complement our Accelerator Engine ICs and utilize our technology we have recently introduced a new Software Accelerator product line that leverages our proprietary graphical memory engine technology to provide data classification capabilities. These new software and IP products are hardware agnostic and operate with or without one of our Accelerator Engine IC products. We expect to begin licensing these products in the first half of 2020.

Our LineSpeed IC product line comprises non-memory, high-speed serialization-deserialization interface, or SerDes I/O, physical layer, or PHY, devices that ensure signal integrity between interfaces which is commonly referred to as clock data recovery, or CDR, or retimer functionality, which perform multiplexing to transition from one speed to another, commonly referred to as Gearbox functionality. These PHY devices reside within optical modules and on networking equipment line cards designed for next-generation Ethernet and optical transport network applications.

Industry Background

The amount of data and the number of data consumers and devices is growing exponentially, driven primarily by commercial and consumer cloud applications, video services, high speed mobile networks, Internet of Things, or IoT, and many other cloud applications. In order to meet these demands, the new cloud infrastructure, including the backbone, edge, access network and data centers, must scale in both speed and intelligence to handle real-time security, bandwidth allocation, and service-level expectations. In addition, workloads or applications delivered at a massive scale from the cloud require flexible and efficient data transmission to optimize resources to enable these applications and lower the overall cost, size and power of the data center. These increased demands strain

communication between onboard IC devices, limiting the data throughput in network switches and routers and the network backbone.

To meet these demands, carrier and enterprise networks are merging with the cloud and are undergoing significant changes and, most significantly, are migrating to packet-based Ethernet networks that enable higher throughput, lower cost and uniform technology across access, core and metro network infrastructure. These networks have been designed to deliver voice and video applications over high-speed Internet services on one converged, efficient and flexible network. These trends require networking systems, especially the high-speed switches, security appliances and routers that primarily comprise these networks, to comply with evolving market requirements and be capable of providing new services and better quality of service while supporting new protocols and standards. Traditional OEM network and telecommunications equipment manufacturers, such as Nokia Corporation, and its subsidiary, Alcatel-Lucent, Cisco Systems, Inc., Tel. LM Ericsson, Fujitsu Ltd., Hitachi Ltd., Huawei Technologies, and Juniper Networks, Inc., as well as new vendors and cloud-service providers, who are delivering a new set of white-box solutions, must offer higher levels of packet forwarding rates, bandwidth density and be optimized to enable higher-density, lower-power data path connectivity in the next generations of their networking systems.

Networking communications, security, video and computing systems throughout the cloud network must operate at higher speed and performance levels, and so require new generations of packet processors and improved memory subsystems to enable system performance. These systems and their component line cards generally need to support aggregate rates of 100 gigabits per second, or Gbps, and above to meet the continued growth in network traffic. Data centers and access equipment that were previously aggregating slower traffic at rates of up to 40Gbps now are being designed to aggregate traffic at 100Gbps, or more. The transition to high-bandwidth networks and the move to 100Gbps and higher rates at the edge (i.e., closer to the networks and users generating data and voice traffic) is underway, and the increase in data rates for these networks is expected to continue to grow rapidly over the coming years.

The systems that our customers build come in various sizes and utilize cards that contain several types of semiconductors. Line cards are found in chassis-based systems that have slots and can contain up to 20 line cards. Our networking and communication system and certain other system customers typically use chassis-based systems. The alternative is systems that contain a single card; these systems are generally referred to as appliances or “pizza boxes.” Cards that typically plug into a server or compute system are generally referred to as accelerator cards. We believe the wider use of these accelerator cards in systems throughout the network, especially at the edge, will expand the market opportunity for our products, as a number of these cards utilize field programmable gate array ICs, or FPGAs, as the packet processor. Our Accelerator Engines are ideally suited to support FPGAs performing these functions. Each line card, or accelerator card, includes one or more processors and multiple memory chips. These processors are complex ICs or IC chipsets that perform high-speed data or packet processing for functions, such as traffic routing, shaping, metering, billing, statistics, detection, steering, security, video processing, monitoring and workload acceleration. The line cards use various types of memory ICs to facilitate temporary packet storage and assist in the analysis and tracking of information embedded within the data flowing through the processors. After a packet enters the line card, a packet or data processor helps separate the packet into smaller pieces for rapid analysis. In a typical packet-based network for example, the data is broken up into the packet header, which contains vital information on packet destination and type, such as the Internet protocol address, and the payload, which contains the data being sent. Generally, the line card operations must occur at full data rates and typically require frequent access to the memory ICs.

Simultaneously, the packet’s payload, which may be substantially larger than the packet header, is also stored in memory ICs until processing is complete and the packet can be re-combined and sent to its next system destination. Within the line card, communication between the packet processor and memory ICs occurs through an interface consisting of combinations of physical pins on each type of chip. These pins are grouped together in a parallel or a serial architecture to form a pathway, called a bus, through which information is transferred from one IC to the next.

Today, the majority of physical buses that connect networking equipment and components use a parallel architecture to communicate between processors and memory ICs, which means information can travel only in one direction and in one instance at a time. As processing speeds increase, the number of pins required and the speed of the bus in a parallel architecture become a limitation on system performance and capability. In contrast, the number of connections is reduced substantially across fewer, higher-rate pins in a serial architecture, and data is transferred

simultaneously in both directions. Data transfer rates are limited by the data access rates of the various ICs included on the line card, thus leading to bottlenecks when these ICs perform inadequately. In order to remove these bottlenecks and meet next-generation bandwidth requirements, the line card ICs need to support higher access rates enabled by internal memory or high-speed serial bus architectures and these more advanced interface protocols.

Most networking and communication systems sold and in operation today include line cards that process data at speeds ranging from 10Gbps to 400Gbps, and support many aggregated slower ports. To accommodate the substantial and growing increase in demand for networking communications and applications, networking systems manufacturers are developing and bringing to market next-generation systems that run at aggregate speeds of 400 Gbps or more with newer products scaling to tens of thousands of Gbps, or tens of terabits, per second. Applications, such as security appliances, broadcast video and compute accelerators that were previously running at aggregate rates of 10Gbps or 40Gbps, are moving to higher aggregate rates in the 100s of Gbps. Although processor performance in applications, such as computing and networking has traditionally doubled nearly every 18 months, or even sooner, the performance of external high-density memory technology has generally been able to double only once every 10 years. Existing memory IC solutions built for high capacity and based on parallel interface architecture struggle to meet the access rates required to meet speeds of 100Gbps and beyond due to system-level limitations for pin counts, power and performance. To compensate for slow external memory access, developers must either integrate larger amounts of on-chip memory and/or utilize complex system alternatives to try to work around the access-rate limitations of these memories. The additional memory and circuitry adds to IC power, size and cost and may not be feasible depending on the economics and technology used to implement the data processor. These networking and communications systems generally comprise a chassis populated by 4 to 16 line cards. Often, these systems are shipped to customers with only a portion of the line card slots populated, and the customer will add additional line cards to increase system performance, capacity and features.

Each line card requires a significant amount of memory to support its processing capabilities. Traditional external memory IC solutions currently used on line cards include both dynamic random access memory, or DRAM, and static random access memory, or SRAM. Line cards in networking systems use both specialized, high-performance DRAM ICs, such as reduced-latency DRAM, or RLDRAM, low-latency DRAM, or LLDRAM, and commodity DRAM, such as double data rate, or DDR ICs. The latest DDR memory is high-bandwidth memory, or HBM, which provides high bandwidth, but has fundamentally slow access time. For very high access, networking systems use higher-performance SRAM, which may be integrated into the data processing IC itself depending on size, power and economics or use traditional external SRAM IC, such as quad data rate, or QDR SRAM. These memories are very fast, but are much smaller, cost more and burn more power than traditional DRAM. Substantially all of these traditional memory IC solutions use parallel interfaces, which are slower than serial interfaces. For data processing solutions, which are unable to integrate large amounts of SRAM, such as field-programmable gate arrays (FPGA), we believe the traditional external SRAMs or RLDRAMs will be increasingly challenged to meet the performance, pin count, area and power requirements as networking systems and other new security, video, and compute systems expand beyond 100Gbps. The result is a gap between processor and memory performance. To meet the higher performance requirements being demanded by the industry, while using current components and architectural approaches, system designers must add more discrete memory ICs to the line cards and/or add more embedded memory on the packet processor. New processor and custom data processing engine ICs are being developed that integrate more SRAM to help offset the bottlenecks, but the cost to develop these custom ICs is high and there is a trade-off in cost, power and size. FPGAs offer flexibility, lower development cost and time to market but are limited in the amount of internal circuitry and the amount of integrated SRAM memory. We believe our Accelerator Engine family of products is well suited to address memory access bottleneck challenges and provide significant performance, size, pin count and power advantages compared to traditional external memory solutions, primarily for FPGA-based systems.

In order to improve performance and resolve memory bottlenecks, in recent years, the trend has been to have algorithms on the memory device perform computations in order to reduce processing time and power consumption. This trend is sometimes called in-memory compute or processor-in-memory. In order to make a flexible solution, the in-memory compute can be accomplished with arrays of reduced instruction set computer, or RISC, cores on the memory device. Further performance gains can be accomplished with application-specific enhancements to the memory device’s instruction set architecture.

We have developed our ICs to synergistically address the need for high-speed data access and throughput currently confronting system designers. We expect our IC products to meet the increasing demands placed on conventional memory technology used on the line cards in high-speed systems. We believe that our products and

technology are well positioned as replacements for existing IC solutions in order to support the needs of a growing number of FPGA-based data processing applications with aggregate rates greater than 100Gbps that require high bandwidth and high access rate to memory.

Our Approach

We have leveraged our proprietary IP to design our IC products and related acceleration IP to help OEMs in our target markets to address the growing bottlenecks in system performance. We have incorporated critical features into our product families to accomplish this objective.

High-Performance Interface

High-speed, efficient interfaces are critical building blocks to meet high data transfer rate requirements for communication between ICs on network line cards. Semiconductor companies are increasingly turning to serial interface architectures to achieve needed system performance. Using serial interfaces, IC developers also are able to reduce the number of pins (the wired electrical pins that connect an IC to the network line card on which it is mounted) on the IC. With reducing geometries, the size of most high-performance ICs is dictated by the number of pins required, rather than the amount of logic and memory embedded in the chip. As a result, using a serial interface facilitates cost reduction and reduced system power consumption, while improving the performance of both the IC itself and the overall system. While serial interfaces provide significantly enhanced performance over parallel interfaces, SerDes interfaces traditionally have had higher power consumption, which is a challenge for IC designers. Our SerDes interfaces, however, are optimized to meet our customers’ signal integrity, low-power consumption and latency requirements.

We make our interface technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering development and validation costs.

GigaChip Interface Protocol

In addition to the physical characteristics of the serial interface, the protocol used to transmit data is also an important element that impacts speed and performance. To address this and complement our Accelerator Engine devices, we have developed the GigaChip Interface, or GCI, which is an open-interface transport protocol optimized for efficient chip-to-chip communications. The GCI electrical interface is compatible with the current industry standards, including 10G and 25G IEEE and OIF interface standards, to simplify electrical interoperability between devices. GCI can enable highly efficient serial chip-to-chip communications, and its transport efficiency averages 90% for the data transfers it handles. GCI is included in our ICs and is offered to customers and prospective partners on terms intended to encourage widespread adoption.

High-Performance and High-Density Memory Architecture

The high density of our proprietary 1T-SRAM technology stems from the use of a single-transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM, or 6T-SRAM. Embedded memory utilizing our 1T-SRAM technologies typically provides speeds essentially equal to or greater than the speeds of traditional SRAM and DRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than DRAM technology. Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generate less heat than traditional SRAM when operating at the same speed. The 1T-SRAM allows us to integrate more high-performance memory using less expensive processing technology, reduce system level heat dissipation and enable reliable operation using lower-cost packaging.

Embedded In-Memory Functions

We have combined our high-speed memory architecture with intelligence to define an embedded memory that can execute embedded functions and algorithms internally, or “in-memory,” to allow software and hardware designers acceleration options to improve the performance of their applications.

The in-memory functions executed within the memory architecture in our Accelerator Engine products result in application-performance increases by reducing the number of external memory and computational operations needed to accomplish the same functions using traditional memories. Also, by executing in-memory, the resources of the packet processor and other ICs on the customer’s board are available to perform other functions.

Our Accelerator Engine ICs include an arithmetic logic unit, or ALU, which enables the performance of mathematical operations on data. Moving certain processing functions from the host data processor IC to the Accelerator Engine IC through the use of this embedded ALU, reduces the number of processing transactions and frees the host data processor IC to perform other important networking or micro-processing functions.

Our Programmable HyperSpeed Engine IC takes this concept one step further by incorporating integrated RISC processors optimized for processing data structures and graphs. Our Programmable HyperSpeed Engine IC integrates RISC cores optimized for operating data stored in the memory block. The integration of the cores with memory allows system algorithms or functions to be offloaded to the device and reduces overall system-task latency and increases throughput. The processors can be programmed by the user to offload and accelerate standard and/or customized functions from the main processor thereby reducing memory transactions and data path complexity to provide improved performance and lower system latency. New algorithms or functions can be added to or modified in the Programmable HyperSpeed Engine IC in software.

Our Strategy

Our primary business objective is to be a profitable IP-rich fabless semiconductor company offering ICs and related software and IP that deliver unparalleled memory bandwidth and access rate performance for high-performance data processing in cloud networking, security appliances, video, test and monitoring, and data center systems. The key components of our strategic plan include the following strategies:

Target Large and Growing Markets

Prior to 2019, our primary focus was the multi-billion dollar networking, telecommunications, security appliance and data center OEM equipment markets, as our products were developed to support the growth in 100Gbps and higher networking speeds. During 2019, we expanded our market focus to new markets, including video, test and measurement and computing markets. We are currently supporting numerous customers across these markets, with whom we have achieved design wins. We define a design win as a commitment from a customer to utilize one of our IC products in its system. We continue to actively pursue additional design wins for the use of our ICs in our target markets. We believe our design wins represent the potential for future revenue growth. However, there is no assurance that these customer designs will be shipped in large volume by our customers to their customers, how much revenue each design win is likely to generate, or how much revenue all of these (and future design wins) are likely to generate.

Build Long-Term Relationships with FPGA Vendors and Suppliers of Data Processing Solutions

We believe that having long-term relationships with FPGA providers is critical to our success, as such relationships enable us to reduce our time-to-market, provide us with a competitive advantage and expand our target markets. A key consideration of network system designers is to demonstrate interoperability between our IC products and the processor ICs utilized in their systems. To obtain design wins, we must demonstrate this interoperability, and also show that our IC works optimally with the packet processor to achieve the performance requirements. In addition, our current strategy requires packet processor suppliers to adopt our GCI interface. To that end, we have been working closely with FPGA and application specific standard product providers to enable interoperability between our Accelerator Engine IC products and their high-performance products. To facilitate the acceptance of our Accelerator Engine ICs, we have made available development and characterization kits for system designers to evaluate and develop code for next-generation networking systems. Our characterization kits are fully-functional hardware platforms that allow FPGA and ASIC providers, and their customers, to demonstrate interoperability of the Accelerator Engine IC with the ASIC or FPGA the designers use within their systems.

Accelerator Engines

Our Accelerator Engine IC products, include the Bandwidth Engine, which is targeted for high-performance applications where throughput is critical, and the Programmable HyperSpeed Engine, which combines the features of the Bandwidth Engine with 32 RISC processors to allow user-defined functions or algorithms to be embedded in the Programmable HyperSpeed Engine.

Bandwidth Engine

The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element. Our Bandwidth Engine ICs combine: (1) our proprietary high-density, high-speed, low latency embedded memory, (2) our high-speed serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM memory and serial interface with logic and other intelligence functions provides a system-level solution and significantly improves overall system performance at lower cost, size and power consumption. Our Bandwidth Engine ICs can provide up to and over 6.5 billion memory accesses per second externally and 12 billion memory accesses per second internally, which we believe is more than three times the performance of current memory-based solutions. They also can enable system designers to significantly narrow the gap between processor and memory IC performance. Our customers that design Bandwidth Engine ICs onto the line cards in their systems will re-architect their systems at the line-card level and use our product to replace traditional memory solutions. When compared with existing commercially available solutions, our Bandwidth Engine ICs may:

• provide up to four times the performance;

• reduce power consumption by approximately 50%;

• reduce cost by greater than 50%; and

• result in a dramatic reduction in IC pin counts on the line card.

Our Bandwidth Engine 2 IC products contain 576 megabits, or Mb, of memory and use a SerDes interface with up to 16 lanes operating at up to 12.5Gbps per lane. We have been shipping our Bandwidth Engine 2 IC products since 2013. We continue to win new designs for this device family, and expect these products to be our primary revenue source for the foreseeable future.

Our Bandwidth Engine 3 IC products contain 1152Mb of memory and use a SerDes interface with up to 16 lanes operating at up to 25Gbps per lane. Our Bandwidth Engine 3 ICs target support for packet-processing applications with up to five billion memory single word accesses per second, as well as burst mode to enable full duplex buffering up to 400 Gbps for ingress, egress and oversubscription applications. The devices provide benefits of size, power, pin count and cost savings to our customers.

Programmable HyperSpeed Engine

Our Programmable HyperSpeed Engine IC products further leverage our proven serial interface technology and high-density integrated memory with the processor engine architecture to enable high-speed customizable search, security, and data analysis functions for networking, security, and data center applications, as well as new markets such as video and compute acceleration. The product architecture features 32 search-optimized processor engines, data flow schedulers, and over a terabit of internal access bandwidth. The device leverages our GCI interface technology and high-density integrated memory (1152Mb of 1T-SRAM embedded memory).

LineSpeed Flex PHYs

Our LineSpeed Flex family of 100G PHYs, is designed to support industry standards and includes gearbox, Multi-Link Gearbox, or MLG, and high density CDR/retimer devices designed to enable Ethernet and OTN line card applications to support the latest electrical and optical interfaces. To date, we have announced four unique devices in this product family:

• MSH320, a 100Gbps Gearbox with RS-FEC: For adapting 10x10Gbps to 4x25Gbps from 100Gbps optical standards to a host ASIC, MAC/Framer, NPU or FPGA with 10x10Gbps interfaces. The MSH320 includes an integrated Reed-Solomon forward error correction, or RS-FEC, option to enable systems to also support 100G electrical and optical standards. The device also includes a 10x10Gbps retimer to allow seamless support of 10 and 40Gbps interfaces;

• MSH225, a 10 Lane Full-Duplex Retimer: For high-density retiming applications where the line rates may be up to 28Gbps per lane and connect to host ASIC, framer, NPU or FPGA ICs equipped with 25Gbps interfaces. Each one of the 20 total independent lanes can be configured to support 10, 25, 40 or 100Gbps standards. The MSH225 integrates optional 100GE RS-FEC capability;

• MSH322, a 100Gbps Multi-Link Gearbox for Line Cards for support of high-density, independent 10GE and 40GE interfaces multiplexed into a 100GE (4x25Gbps) host interface, while supporting electrical and optical industry standards. The device enables line cards with high-density switches based on 25Gbps interfaces to support two times the density of 10 and 40Gbps ports; and

• MSH321, a derivative Multi-Link Gearbox built into a highly compact package and optimized layout to support the MLG function in module and compact daughter card applications.

IP Licensing

Historically, we licensed our IT-SRAM memory and SerDes interface technologies on a worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies. Most of these licensees incorporated our technology into ICs that they sold to their customers, and, in the case of IT-SRAM licenses, pay a royalty to us for each IC shipped that incorporates our technology. Royalty and other revenue generated from our legacy IP agreements represented 7%, 9% and 11% of our total revenues for 2019, 2018 and 2017, respectively.

Recently, we announced our new Software Accelerator product line consisting of software and IP available for license. This new product line will include multiple function accelerator platform products, which target specific application functions and will use a common software interface to allow performance scalability over multiple hardware environments. These function accelerator platform products are hardware agnostic and operate with or without one of our Accelerator Engine ICs. This software-defined, hardware-accelerated platform architecture utilizes an internally developed graphical memory engine architecture to provide flexible data classification and analysis capability. We believe the technology will generate new opportunities that require less up-front architectural changes by system designers and provide a scalable performance roadmap of options using our Accelerator Engine ICs. We expect our initial Software Accelerator products to be available for license in the first half of 2020.

Research and Development

Our ability to compete in the future depends on successfully improving our technology to meet the market’s increasing demand for higher performance and lower cost solutions. Development of new IC products requires specialized chip design and product engineers, as well as significant fabrication and testing costs, including mask costs. We currently do not have internal resources for new IC products. That said, we believe our Accelerator Engine IC product portfolio will provide us with adequate revenue growth opportunity for the foreseeable future. We have focused our product development efforts on software-based capabilities and features that leverage our current technologies and core competencies, as well as our Accelerator Engine IC products. As discussed above, we recently announced our Software Accelerator product line, and the initial packet classification products will use our graph memory engine for performing embedded search and classification of packet headers. We intend to continue to devote the majority of our research and development efforts toward furthering the software accelerator product roadmap.

We believe that systems OEMs typically prefer to extend the use of traditional memory solutions and their parallel interfaces, despite performance and costs challenges, and are reluctant to change their technology platforms and adopt new designs and technologies, such as serial interfaces, which are an integral part of our product solutions. Therefore, our principal selling and marketing activities to date have been focused on persuading these OEMs and key component specialists that our IC products provide critical performance advantages, as well as on securing design wins with them.

In addition to our direct sales personnel, we sell through sales representatives and distributors in the United States and Asia. We also have applications engineers who support our customer engagements and engage with the customers’ system architects and designers to propose and implement our IC and IP solutions to address system design challenges.

In the markets we serve, the time from a design win to production volume shipments of our IC products can range from 18 to 36 months. Networking, communications and security appliance systems can have a product life from a few years to over 10 years once a product like ours has been designed into the system.

Our revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue. For the year ended December 31, 2019, Flextronics, which primarily purchases on behalf of Palo Alto Networks, Inc. and Nokia; Clavis Company our Japanese IC distributor; Sanmina and Palo Alto Networks, represented 30%, 17%, 14% and 13% of total revenue, respectively. For the year ended December 31, 2018, Flextronics, which primarily purchases on behalf of Palo Alto Networks, Inc. and Nokia; Clavis Company, our Japanese IC distributor; Palo Alto Networks; and Nokia, represented 32%, 18%, 18% and 15% of total revenue, respectively.

Intellectual Property

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of December 31, 2019, we held 62 U.S. and 34 foreign patents on various aspects of our technology, with expiration dates ranging from 2021 to 2037. We also held 6 pending patent applications in the U.S. and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, “Risk Factors.”

Competition

The markets for our products are highly competitive. We believe that the principal competitive factors are:

• processing speed and performance;

• density and cost;

• power consumption;

• reliability;

• interface requirements;

• ease with which technology can be customized for and incorporated into customers’ products; and

• level of technical support provided.

We believe that our products compete favorably with respect to each of these criteria. Our proprietary 1T-SRAM embedded memory and high-speed serial interface IP can provide our Accelerator Engine ICs with a competitive advantage over alternative devices. Alternative solutions are either DRAM or SRAM-based and can support either the memory size or speed requirements of high-performance networking systems, but generally not both. DRAM solutions provide a significant amount of memory at competitive cost, but DRAM solutions do not have the required fast access and cycle times to enable high-performance. The DRAM solutions currently used in networking systems include RLDRAM from Micron Technology, Inc., or Micron, LLDRAM from Renesas, DDR from Samsung Electronics Co., Ltd., Micron and others, and HBM, which is stacked memory from Samsung Electronics Co. and SK Hynix. SRAM solutions can meet high-speed performance requirements, but often lack adequate memory size. The SRAM solutions currently used in networking systems primarily include QDR or similar SRAM products from Cypress Semiconductor Corporation and GSI Technology, Inc. Most of the currently available SRAM and DRAM solutions use a parallel, rather than a serial interface. To offset these drawbacks, system designers generally must use more discrete memory ICs, resulting in higher power consumption and greater utilization of space on the line card.

Our competitors include established semiconductor companies with significantly longer operating histories, greater name recognition and reputation, large customer bases, dedicated manufacturing facilities and greater financial, technical, sales and marketing resources. This may allow them to respond more quickly than us to new or emerging technologies or changes in customer requirements. Generally, customers prefer suppliers with greater financial resources than we have currently. Many of our competitors also have significant influence in the semiconductor industry. They may be able to introduce new technologies or devote greater resources to the development, marketing and sales of their products than we can. Furthermore, in the event of a manufacturing capacity shortage, these competitors may be able to manufacture products when we are unable to do so.

Our Accelerator Engine ICs compete with embedded memory solutions, stand-alone memory ICs, including both DRAM and SRAM ICs, ASICs designed by customers in-house to meet their system requirements, and NPUs that use significant internal memory and customer-designed software to implement tasks. Our prospective customers may be unwilling to adopt and design-in our ICs due to the uncertainties and risks surrounding designing a new IC into their systems and relying on a supplier that has limited history of manufacturing such ICs and limited financial resources. In addition, Accelerator Engine ICs require the customer and its other IC suppliers to implement our chip-to-chip communication protocol, the GCI interface. These parties may be unwilling to do this if they believe it could adversely impact their own future product developments or competitive advantages, or, if they believe it might complicate their development process or increase the cost of their products. To remain competitive, we believe we must provide unparalleled memory IC solutions with the highest bandwidth capability for our target markets, which solutions are engineered and built for high-reliability carrier and enterprise applications.

Our LineSpeed PHY ICs compete with solutions offered by Broadcom Ltd., Inphi Corporation, M/A-COM Technology Solutions Holdings, Inc. and Semtech Corp., as well as other smaller analog signal processing companies. We also may compete with ASICs designed by customers in-house to meet their system requirements, as well as by optical module OEMs. The market for our LineSpeed products is highly competitive, and customers have a number of suppliers they can choose from. We must provide differentiated features with a reasonable IC power budget, while offering competitive pricing. To date, we have had limited success selling and marketing these products.

Manufacturing

We depend on third-party vendors to manufacture, package, assemble and test our IC products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility. By outsourcing manufacturing, we can avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

We perform an ongoing review of our product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meets design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers. We have achieved ISO 9001:2015 certification, and all of our significant manufacturing vendors have also achieved ISO 9001 certification.

Employees

As of December 31, 2019, we had 23 employees all of whom are located in the United States, consisting of 14 in research and development and manufacturing operations and 9 in sales, marketing and general and administrative functions.

Available Information

We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934, as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read any materials submitted electronically by us to the SEC on its website (www.sec.gov), which contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Overview

MoSys, Inc., together with its subsidiaries (“MoSys,” the “Company,” “we,” “our” or “us”), is a fabless semiconductor company focused on the development and sale of integrated circuits, or ICs, for the high-speed cloud networking, communications, security appliance, video, monitor and test, data center and computing markets. Our solutions deliver time-to-market, performance, power, area and economic benefits for system original equipment manufacturers, or OEMs. Our primary product line is marketed under the Blazar Accelerator Engine name and comprises our Bandwidth Engine and Programmable HyperSpeed Engine, or PHE, IC products, which integrate our proprietary, 1T-SRAM high-density embedded memory and a highly-efficient serial interface protocol resulting in a monolithic memory IC solution optimized for memory bandwidth and transaction access performance. Further performance benefits can be achieved to offload statistical, search or other custom functions using our optional integrated logic and processor elements. As data rates and the amount of high-speed processing increase, critical memory access bottlenecks occur. Our Bandwidth Engine and PHE ICs dramatically increase memory accesses per second, removing these bottlenecks. In addition, the serial interface and high-memory capacity reduce the board footprint, number of pins and complexity, while using less power. Our LineSpeed IC product line comprises non-memory, high-speed serialization-deserialization interface, or SerDes I/O, physical layer, or PHY, devices that ensure signal integrity between interfaces which is commonly referred to as clock data recovery, or CDR, or retimer functionality, which perform multiplexing to transition from one speed to another, commonly referred to as Gearbox functionality. These PHY devices reside within optical modules and networking equipment line cards designed for next-generation Ethernet and optical transport network applications.

Industry Background

The amount of data and the number of data consumers and devices is growing exponentially, driven primarily by commercial and consumer cloud applications, video services, high speed mobile networks, Internet of Things, or IoT, and many other cloud applications. In order to meet these demands, the new cloud infrastructure, including the backbone, edge, access network and data centers, must scale in both speed and intelligence to handle real-time security, bandwidth allocation, and service-level expectations. In addition, workloads or applications delivered at a massive scale from the cloud require flexible and efficient data transmission to optimize resources to enable these applications and lower the overall cost, size and power of the data center. These increased demands strain communication between onboard IC devices, limiting the data throughput in network switches and routers and the network backbone.

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To meet these demands, carrier and enterprise networks are merging with the cloud and are undergoing significant changes and, most significantly, are migrating to packet-based Ethernet networks that enable higher throughput, lower cost and uniform technology across access, core and metro network infrastructure. These networks are now being designed to deliver voice, video and high-speed Internet services on one converged, efficient and flexible network. These trends require networking systems, especially the high-speed switches, security appliances and routers that primarily comprise these networks, to comply with evolving market requirements and be capable of providing new services and better quality of service while supporting new protocols and standards. To support these trends, traditional OEM network and telecommunications equipment manufacturers, such as Nokia Corporation, and its subsidiary, Alcatel-Lucent, Cisco Systems, Inc., Tel. LM Ericsson, Fujitsu Ltd., Hitachi Ltd., Huawei Technologies, and Juniper Networks, Inc., as well as new vendors and cloud-service providers, who are delivering a new set of white-box solutions, must offer higher levels of packet forwarding rates, bandwidth density and be optimized to enable higher-density, lower-power data path connectivity in the next generations of their networking systems.

Networking communications, security, video and computing systems throughout the cloud network must operate at higher speed and performance levels, and so require new generations of packet processors and improved memory subsystems to enable system performance. These systems and their component line cards generally need to support aggregate rates of 100 gigabits per second, or Gbps, and above to meet the continued growth in network traffic. Data centers and access equipment that were previously aggregating slower traffic at rates of up to 40 Gbps now are being designed to aggregate traffic at 100 Gbps, or more. The transition to 100 Gbps networks is underway, and the increase in data rates for these networks is expected to continue to grow rapidly over the coming years.

Several types of semiconductors are included on each line card, including one or more processors and multiple memory chips. These processors are complex ICs or IC chipsets that perform high-speed data or packet processing for functions, such as traffic routing, shaping, metering, billing, statistics, detection, steering, security, video processing, monitoring and workload acceleration. The line cards use various types of memory ICs to facilitate temporary packet storage and assist in the analysis and tracking of information embedded within the data flowing through the processors. After a packet enters the line card, a packet or data processor helps separate the packet into smaller pieces for rapid analysis. In a typical packet-based network for example, the data is broken up into the packet header, which contains vital information on packet destination and type, such as the Internet protocol address, and the payload, which contains the data being sent. Generally, the line card operations must occur at full data rates and typically require accessing memory ICs many times. Simultaneously, the packet’s payload, which may be substantially larger than the packet header, is also stored in memory ICs until processing is complete and the packet can re-combine and be sent to its next system destination. Within the line card, communication between the packet processor and memory ICs occurs through an interface consisting of combinations of physical pins on each type of chip. These pins are grouped together in a parallel or a serial architecture to form a pathway, called a bus, through which information is transferred from one IC to the next.

Today, the majority of physical buses that connect networking equipment and components use a parallel architecture to communicate between processors and memory ICs, which means information can travel only in one direction and in one instance at a time. As processing speeds increase, the number of pins required and the speed of the bus in a parallel architecture become a limitation on system performance and capability. In contrast, the number of connections is reduced substantially across fewer, higher-rate pins in a serial architecture, and data is transferred simultaneously in both directions. Data transfer rates are limited by the data access rates of the various ICs included on the line card, thus leading to bottlenecks when these ICs perform inadequately. In order to remove these bottlenecks and meet next-generation bandwidth requirements, the line card ICs need to support higher access rates enabled by internal memory or high-speed serial bus architectures and these more advanced interface protocols.

Most networking and communication systems sold and in operation today include line cards that process data at speeds ranging from 10 Gbps to 400 Gbps, and support many aggregated slower ports. To accommodate the substantial and growing increase in demand for networking communications and applications, networking systems manufacturers are developing and bringing to market next-generation systems that run at aggregate speeds of 400 Gbps or more with newer products scaling to tens of thousands of Gbps, or tens of terabits, per second. Applications, such as security appliances, broadcast video, compute accelerators etc. that were previously running at aggregate rates of 10G or 40G, are moving to higher aggregate rates in the 100s of gigabits. Although processor performance in applications, such as computing and networking has traditionally doubled nearly every 18 months, or even sooner,

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the performance of external high-density memory technology has generally been able to double only once every 10 years. Existing memory IC solutions built for high capacity and based on parallel interface architecture struggle to meet the access rates required to meet speeds of 100 Gbps and beyond due to system-level limitations for pin counts, power and performance. To compensate for slow external memory access, developers must either integrate larger amounts of on-chip memory and/or utilize complex system alternatives to try to work around the access-rate limitations of these memories. The additional memory and circuitry adds to IC power, size and cost and may not be feasible depending on the economics and technology used to implement the data processor. These networking and communications systems generally comprise a chassis populated by four to 16 line cards. Often, these systems are shipped to customers with only a portion of the line card slots populated, and the customer will add additional line cards to increase system performance, capacity and features.

Each line card requires a significant amount of memory to support its processing capabilities. Traditional external memory IC solutions currently used on line cards include both dynamic random access memory, or DRAM, and static random access memory, or SRAM. Line cards in networking systems use both specialized, high-performance DRAM ICs, such as reduced-latency DRAM, or RLDRAM, low-latency DRAM, or LLDRAM, and commodity DRAM, such as double data rate, or DDR ICs. The latest DDR memory is high-bandwidth memory, or HBM, provides high bandwidth, but has fundamentally slow access time. For very high access, networking systems use higher-performance SRAM, which may be integrated into the data processing IC itself depending on size, power and economics or using traditional external SRAM IC, such as quad data rate, or QDR SRAM. These memories are very fast, but are much smaller, cost more and burn more power than traditional DRAM. Substantially all of these traditional memory IC solutions use parallel interfaces, which are slower than serial interfaces. For data processing solutions, which are unable to integrate large amounts of SRAM, such as field-programmable gate arrays (FPGA), we believe the traditional external SRAMs or RLDRAMs will be increasingly challenged to meet the performance, pin count, area and power requirements as networking systems and other new security, video, and compute systems expand beyond 100 Gbps. The result is a gap between processor and memory performance. To meet the higher performance requirements being demanded by the industry, while using current components and architectural approaches, system designers must add more discrete memory ICs to the line cards and/or add more embedded memory on the packet processor. New processor and custom data processing engine ICs are being developed that integrate more SRAM to help offset the bottlenecks, but the cost to develop these custom ICs is high and there is a trade-off in cost, power and size. FPGAs offer flexibility, lower development cost and time to market but are limited in the amount of internal circuitry and the amount of integrated SRAM memory. We believe our Bandwidth Engine family of products is well suited to address memory access bottleneck challenges and provide significant performance, size, pin count and power advantages compared to traditional external memory solutions, especially for FPGA-based systems.

In order to improve performance and resolve memory bottlenecks, there is an emerging trend in which computations are performed by algorithms on the memory device in order to reduce processing time and power consumption. This trend is sometimes called in-memory compute or processor-in-memory. In order to make a flexible solution, the in-memory compute can be accomplished with arrays of reduced instruction set computer (RISC) cores on the memory device. Further performance gains can be accomplished with application-specific enhancements to the memory device’s instruction set architecture.

We have developed our ICs to synergistically address the need for high-speed data access and throughput currently confronting system designers. We expect our IC products to meet the increasing demands placed on conventional memory technology used on the line cards in high-speed systems. We believe that our products and technology are well positioned as replacements for existing IC solutions in order to support the needs of a growing number of FPGA-based data processing applications with aggregate rates greater than 100 Gbps that require high bandwidth and high access rate to memory.

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We have leveraged our proprietary intellectual property, or IP, to design our IC products to help networking OEMs address the growing bottlenecks in system performance. We have incorporated critical features into our product families to accomplish this objective.

On-Chip Acceleration

One significant performance bottleneck in any network line card is the need to transfer data between discrete ICs. Many of these data-transfer operations are iterative in nature, requiring subsequent, back-to-back accesses of the memory IC by the processor IC. Our Bandwidth Engine ICs include an arithmetic logic unit, or ALU, which enables the performance of mathematical operations on data. Moving certain processing functions from the processor IC to the Bandwidth Engine IC through the use of this embedded ALU, reduces the number of processing transactions and frees the processor IC to perform other important networking or micro-processing functions.

The PHE, which we formerly called our programmable search engine, or PSE IC, takes this concept one step further by incorporating integrated RISC processors optimized for processing data structures and graphs. The processors can be programmed by the user to offload and accelerate standard and/or customized functions from the main processor thereby reducing memory transactions and data path complexity to provide improved performance and lower system latency.

High-Performance Interface

High-speed, efficient interfaces are critical building blocks to meet high data transfer rate requirements for communication between ICs on network line cards. Semiconductor companies are increasingly turning to serial interface architectures to achieve needed system performance. For example, high-performance ICs that are sold into wide markets, such as field programmable gate arrays, or FPGAs, and network processing units, NPUs, are using serial interfaces to ensure they can compete with custom designed application specific ICs, or ASICs, by matching their performance. Using serial interfaces, IC developers also are able to reduce pin count (the wired electrical pins that connect an IC to the network line card on which it is mounted) on the IC. With reducing geometries, the size of most high-performance ICs is dictated by the number of pins required, rather than the amount of logic and memory embedded in the chip. As a result, using serial interface facilitates cost reduction and reduced system power consumption, while improving the performance of both the IC itself and the overall system. While serial interfaces provide significantly enhanced performance over parallel interfaces, SerDes interfaces traditionally have had higher power consumption, which is a challenge for IC designers. Our SerDes interfaces, however, are optimized to meet our customers’ signal integrity, low-power consumption and latency requirements.

We make our interface technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering development and validation costs. Interoperability reduces development time, thereby reducing the overall time to market of our customers’ systems.

GigaChip Interface Protocol

In addition to the physical characteristics of the serial interface, the protocol used to transmit data is also an important element that impacts speed and performance. To address this and complement our Bandwidth Engine and PHE devices, we have developed the GigaChip Interface, or GCI, which is an open-interface transport protocol optimized for efficient chip-to-chip communications. The GCI electrical interface is compatible with the current industry standards, including 10G and 25G IEEE and OIF interface standards, to simplify electrical interoperability between devices. GCI can enable highly efficient serial chip-to-chip communications, and its transport efficiency averages 90% for the data transfers it handles. GCI is included in our ICs and is offered to customers and prospective partners on terms intended to encourage widespread adoption.

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High-Performance and High-Density Memory Architecture

The high density of our proprietary 1T-SRAM technologies stems from the use of a single-transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM, or 6T-SRAM. Embedded memory utilizing our 1T-SRAM technologies typically provides speeds essentially equal to or greater than the speeds of traditional SRAM and DRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than DRAM technology. Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generate less heat than traditional SRAM when operating at the same speed. The 1T-SRAM allows us to integrate more high-performance memory using less expensive processing technology, reduces system level heat dissipation and enables reliable operation using lower-cost packaging.

Our PHE integrates RISC cores optimized for operating data stored in the PHE’s memory block. The integration of the cores with memory allows system algorithms or functions to be offloaded to the device and reduces overall system-task latency and increases throughput. New algorithms or functions can be added or adjusted to the PHE device in software.

Embedded In-Memory Functions (IMF)

We have combined our high-speed memory architecture with intelligence to define an embedded memory that can execute embedded functions and algorithms internally, or “in-memory,” to allow software and hardware designers acceleration options to improve the performance of their applications.

The IMFs executed within the memory architecture in our Bandwidth Engine and PHE products result in application-performance increases by reducing the number of external memory and computational operations need to accomplish the same functions using traditional memories. Also, by executing in-memory, the resources of the packet processor and other ICs on the customer’s board are available to perform other functions.

Our Strategy

Our primary business objective is to be a profitable IP-rich fabless semiconductor company offering ICs that deliver unparalleled memory bandwidth and access rate performance for high-performance data processing in cloud networking, security appliances, video, test and monitoring, and data center systems. The key components of our strategic plan include the following strategies:

Target Large and Growing Markets

Our initial strategy is to target the multi-billion dollar networking, telecommunications, security appliance and data center OEM equipment markets, and we have developed products to support the growth in 100 Gbps and higher networking speeds. We are currently supporting numerous customers, with whom we have achieved design wins. We continue to actively pursue additional design wins for the use of our ICs in our target markets. We believe our design wins represent the potential for future revenue growth. With limited history to date, however, we cannot estimate how much revenue each design win is likely to generate, or how much revenue all of these (and future design wins) are likely to generate. There is no assurance that these customer designs will be shipped in large volume by our customers to their customers, however.

Expand Adoption of the GigaChip Interface Protocol

We have provided our GCI interface protocol as an open industry standard that may be designed into other ICs in the system, as we believe this will further enable serial communication on line cards and encourage adoption of our Bandwidth Engine IC products. A number of IC providers and partners have publicly announced their support of GCI and Bandwidth Engine, including the largest FPGA providers -Altera Corporation (a subsidiary of Intel Corporation) and Xilinx, Inc., and EZchip Semiconductor Ltd. (a subsidiary of Mellanox Technologies Ltd.), with whom we work closely to support common customers. In addition, multiple networking systems companies, including actual and prospective customers, have adopted GCI.

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Build Long-Term Relationships with FPGA Vendors and Suppliers of Data Processing Solutions

We believe that having long-term relationships with FPGA providers is critical to our success, as such relationships enable us to reduce our time-to-market, provide us with a competitive advantage and expand our target markets. A key consideration of network system designers is to demonstrate interoperability between our IC products and the processor ICs utilized in their systems. To obtain design wins, we must demonstrate this interoperability, and also show that our IC works optimally with the packet processor to achieve the performance requirements. In addition, our current strategy requires packet processor suppliers to adopt our GCI interface. To that end, we have been working closely with FPGA and application specific standard product providers, to enable interoperability between our Bandwidth Engine IC products and their high-performance products. To facilitate the acceptance of our Bandwidth Engine ICs, we have made available development and characterization kits for system designers to evaluate and develop code for next-generation networking systems. Our characterization kits are fully-functional hardware platforms that allow FPGA and ASIC providers, and their customers, to demonstrate interoperability of the Bandwidth Engine IC with the ASIC or FPGA the designers use within their systems.

Our IC Products

BLAZAR Accelerator Engines

Our Blazar Accelerator Engines, include the Bandwidth Engine, which is targeted for high-performance applications where throughput is critical, and the PHE, which combines the features of the Bandwidth Engine with 32 RISC processors to allow user-defined functions or algorithms to be embedded in the PHE.

Bandwidth Engine

The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element. Our Bandwidth Engine ICs combine: (1) our proprietary high-density, high-speed, low latency embedded memory, (2) our high-speed serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM memory and serial interface with logic and other intelligence functions provides a system-level solution and significantly improves overall system performance at lower cost, size and power consumption. Our Bandwidth Engine ICs can provide up to and over 6.5 billion memory accesses per second externally and 12 billion memory accesses per second internally, which is more than three times the performance of current memory-based solutions. They also can enable system designers to significantly narrow the gap between processor and memory IC performance. Customers that design Bandwidth Engine ICs onto the line cards in their networking systems will re-architect their systems at the line-card level and use our product to replace traditional memory solutions. When compared with existing commercially available solutions, our Bandwidth Engine ICs may:

• provide up to four times the performance;

• reduce power consumption by approximately 50%;

• reduce cost by greater than 50%; and

• result in a dramatic reduction in IC pin counts on the line card.

Our first-generation Bandwidth Engine IC products contain 576 megabytes, or MB, of memory and use a serial interface with up to 16 lanes operating at up to 10.3 Gbps per lane. We announced the end-of-life of these products and expect to complete fulfillment of last-time customer orders in the first half of 2019.

Our second-generation Bandwidth Engine IC products contain 576 MB of memory and use a SerDes interface with up to 16 lanes operating at up to 12.5 Gbps per lane. In addition to a speed improvement of up to 50% over our first-generation products, the architecture has enabled multiple family-member parts with added specialized features. We have been shipping our Bandwidth Engine 2 IC products since 2013. We continue to win new designs for this device family, and expect these products to be our primary revenue source for the foreseeable future.

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Our third-generation Bandwidth Engine IC products contain 1152 MB of memory and use a SerDes interface with up to 16 lanes operating at up to 25 Gbps per lane. Our Bandwidth Engine 3 ICs target support for packet-processing applications with up to five billion memory single word accesses per second, as well as burst mode to enable full duplex buffering up to 400 Gbps for ingress, egress and oversubscription applications. The devices provide benefits of size, power, pin count and cost savings to our customers. We do not anticipate customer production revenues from these products until the second half of 2019 or later.

Programmable HyperSpeed Engine (PHE)

Our PHE IC products further leverage our proven serial interface technology and high-density integrated memory with the processor engine architecture to enable high-speed customizable search, security, and data analysis functions for networking, security, and data center applications, as well as new markets such as video and compute acceleration. Our PHE architecture features 32 search-optimized processor engines, data flow schedulers, and over a terabit of internal access bandwidth. The device leverages our GCI interface technology and high-density integrated memory (1152 Mb of 1T-SRAM embedded memory).

LineSpeed Flex PHYs

Our LineSpeed Flex family of 100G PHYs, is designed to support industry standards and includes gearbox, Multi-Link Gearbox, or MLG, and high density CDR/retimer devices designed to enable Ethernet and OTN line card applications to support the latest electrical and optical interfaces. To date, we have announced four unique devices in this product family:

• MSH320, a 100Gbps Gearbox with RS-FEC: For adapting 10x10 to 4x25 from 100Gbps optical standards to a host ASIC, MAC/Framer, NPU or FPGA with 10x10G interfaces. The MSH320 includes an integrated Reed-Solomon forward error correction, or RS-FEC, option to enable systems to also support 100G electrical and optical standards. The device also includes a 10x10Gbps retimer to allow seamless support of 10 and 40Gbps interfaces;

• MSH225, a 10 Lane Full-Duplex Retimer: For high-density retiming applications where the line rates may be up to 28Gbps per lane and connect to host ASIC, framer, NPU or FPGA ICs equipped with 25Gbps interfaces. Each one of the 20 total independent lanes can be configured to support 10, 25, 40 or 100Gbps standards. The MSH225 integrates optional 100Gbps RS-FEC capability;

• MSH322, a 100Gbps Multi-Link Gearbox for Line Cards for support of high-density, independent 10GE and 40GE interfaces multiplexed into a 100GE (4x25Gbps) host interface, while supporting electrical and optical industry standards. The device enables line cards with high-density switches based on 25Gbps interfaces to support two times the density of 10 and 40Gbps ports; and

• MSH321, a derivative Multi-Link Gearbox built into a highly compact package and optimized layout to support the MLG function in module and compact daughter card applications.

We are shipping production quantities of our LineSpeed products to a lead customer, and expect to begin generating meaningful recurring revenue from sales to this customer in 2019.

IP Licensing and Distribution

Historically, we have offered our memory and interface technologies on a worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies through product development, technology licensing and joint marketing relationships. We licensed our IP technology to semiconductor companies who incorporated our technology into ICs that they sold to their customers. As a result of the change in our corporate strategy, since early 2012, our IP licensing activities have been limited, and we expect this to continue. Royalty and other revenue generated from our existing IP agreements represented 9%, 11% and 24% of our total revenue in 2018, 2017 and 2016, respectively. Royalty revenues have been declining since 2010, and we expect them to continue to decline in 2019.

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Our ability to compete in the future depends on successfully improving our technology to meet the market’s increasing demand for higher performance and lower cost solutions. Development of our IC products requires specialized chip design and product engineers, as well as significant fabrication and testing costs, including mask costs, as we bring these products to market. During 2017, we substantially reduced our headcount, and currently have limited internal resources available for new IC product development, which will result in fewer product improvements and new developments. In the near term, our planned product roadmap will include software-based capabilities and features that leverage our existing base of IC products.

Sales and Marketing

We believe that systems OEMs typically prefer to extend the use of traditional memory solutions and their parallel interfaces, despite performance and costs challenges, and are reluctant to change their technology platforms and adopt new designs and technologies, such as serial interfaces, which are an integral part of our product solutions. Therefore, our principal selling and marketing activities to date have been focused on persuading these OEMs and key component specialists that our solutions provide critical performance advantages, as well as on securing design wins with them.

In addition to our direct sales personnel, we sell through sales representatives and distributors in the United States and Asia. We also have applications engineers who support our customer engagements and engage with the customers’ system architects and designers to propose and implement our IC and IP solutions, such as the GCI interface, to address their systems challenges.

In the markets we serve, the time from a design win to production volume shipments can range from 18 to 36 months. Networking, communications and security appliance systems can have a product life from a few years to over 10 years once a product like ours has been designed into the system.

Our revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue. For the year ended December 31, 2018, Flextronics, which primarily purchases on behalf of Palo Alto Networks, Inc. and Nokia, formerly Alcatel-Lucent, Clavis Company, formerly Kogent, our Japanese IC distributor, Palo Alto Networks and Nokia, represented 32%, 18%, 18% and 15% of total revenue, respectively. For the year ended December 31, 2017, Flextronics, Clavis Company, and Nokia, represented 46%, 17% and 11% of total revenue, respectively. For the year ended December 31, 2016, Alcatel-Lucent, Clavis Company and Taiwan Semiconductor Manufacturing Co., Ltd., or TSMC, represented 47%, 21% and 13% of our total revenue, respectively.

Intellectual Property

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success, and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of December 31, 2018, we held 67 U.S. and 42 foreign patents on various aspects of our technology, with expiration dates ranging from 2019 to 2036. We also held 8 pending patent applications in the U.S. and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, “Risk Factors.”

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The markets for our products are highly competitive. We believe that the principal competitive factors are:

• processing speed and performance;

• density and cost;

• power consumption;

• reliability;

• interface requirements;

• ease with which technology can be customized for and incorporated into customers’ products; and

• level of technical support provided.

We believe that our products compete favorably with respect to each of these criteria. Our proprietary 1T-SRAM embedded memory and high-speed serial interface IP can provide our Bandwidth Engine ICs with a competitive advantage over alternative devices. Alternative solutions are either DRAM or SRAM-based and can support either the memory size or speed requirements of high-performance networking systems, but generally not both. DRAM solutions provide a significant amount of memory at competitive cost, but DRAM solutions do not have the required fast access and cycle times to enable high-performance. The DRAM solutions currently used in networking systems include RLDRAM from Micron Technology, Inc., or Micron, LLDRAM from Renesas, DDR from Samsung Electronics Co., Ltd., Micron and others, and HBM, which is stacked memory from Samsung Electronics Co. and SK Hynix. SRAM solutions can meet high-speed performance requirements, but often lack adequate memory size. The SRAM solutions currently used in networking systems primarily include QDR or similar SRAM products from Cypress Semiconductor Corporation and GSI Technology, Inc. Most of the currently available SRAM and DRAM solutions use a parallel, rather than a serial interface. To offset these drawbacks, system designers generally must use more discrete memory ICs, resulting in higher power consumption and greater utilization of space on the line card.

Our competitors include established semiconductor companies with significantly longer operating histories, greater name recognition and reputation, large customer bases, dedicated manufacturing facilities and greater financial, technical, sales and marketing resources. This may allow them to respond more quickly than us to new or emerging technologies or changes in customer requirements. Generally, customers prefer suppliers with greater financial resources than we have currently. Many of our competitors also have significant influence in the semiconductor industry. They may be able to introduce new technologies or devote greater resources to the development, marketing and sales of their products than we can. Furthermore, in the event of a manufacturing capacity shortage, these competitors may be able to manufacture products when we are unable to do so.

Our Bandwidth Engine and PHE ICs compete with embedded memory solutions, stand-alone memory ICs, including both DRAM and SRAM ICs, ASICs designed by customers in-house to meet their system requirements, and NPUs that use significant internal memory and customer-designed software to implement tasks. Our prospective customers may be unwilling to adopt and design-in our ICs due to the uncertainties and risks surrounding designing a new IC into their systems and relying on a supplier that has limited history of manufacturing such ICs and limited financial resources. In addition, Bandwidth Engine and PHE ICs require the customer and its other IC suppliers to implement our chip-to-chip communication protocol, the GCI interface. These parties may be unwilling to do this if they believe it could adversely impact their own future product developments or competitive advantages, or, if they believe it might complicate their development process or increase the cost of their products. To remain competitive, we believe we must provide unparalleled memory IC solutions with the highest bandwidth capability for our target markets, which solutions are engineered and built for high-reliability carrier and enterprise applications.

Our LineSpeed PHY ICs compete with solutions offered by Broadcom Ltd., Inphi Corporation, M/A-COM Technology Solutions Holdings, Inc. and Semtech Corp., as well as other smaller analog signal processing companies. We also may compete with ASICs designed by customers in-house to meet their system requirements, as well as by optical module OEMs. The market for our LineSpeed products is highly competitive, and customers have a number of suppliers they can choose from. We must provide differentiated features with a reasonable IC power budget, while offering competitive pricing.

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We depend on third-party vendors to manufacture, package, assemble and test our IC products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility for boards and system assembly. By outsourcing manufacturing, we can avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

We perform an ongoing review of product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meets design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers. We have achieved ISO 9001:2015 certification, and all of our significant manufacturing vendors have also achieved ISO 9001 certification.

Employees

As of December 31, 2018, we had 21 employees all of whom are located in the United States, consisting of 13 in research and development and manufacturing operations and 8 in sales, general and administrative functions.

Available Information

We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934, as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read any materials submitted electronically by us to the SEC on its website (www.sec.gov), which contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

MoSys, Inc., together with its subsidiaries (“MoSys,” the “Company,” “we,” “our” or “us”), is a fabless semiconductor company focused on the development and sale of integrated circuits, or ICs, for the high-speed cloud networking, communications, security appliance, video, monitor and test, data center and computing markets. Our solutions deliver time-to-market, performance, power, area and economic benefits for system original equipment manufacturers, or OEMs. Our primary product line is marketed under the Bandwidth Engine and Programmable Search Engine names and marks, and these IC products integrate our proprietary, 1T-SRAM® high-density embedded memory and a highly-efficient serial interface protocol resulting in a monolithic memory IC solution optimized for memory bandwidth and transaction access performance. Further performance benefits can be achieved to offload statistical, search or other custom functions using our optional integrated logic and processor elements. As data rates and the amount of high-speed processing increase, critical memory access bottlenecks occur. Our Bandwidth Engine, or BE, and Programmable Search Engine, or PSE, ICs drastically increase memory accesses per second, removing these bottlenecks. In addition, the serial interface and high-memory capacity reduce the board footprint, number of pins and complexity, while using less power.

In April 2017, we implemented restructuring initiatives to effect a reduction in our workforce and associated operating expenses, net loss and cash burn. Under these initiatives, we significantly reduced our headcount, closed international sales offices and relocated and downsized our corporate headquarters. We are primarily focusing our resources on producing and selling our existing products, and have substantially curtailed new product development. Despite the reduction in new product development, we believe our current product portfolio and roadmap position us for future growth and profitability. We will continue to seek opportunities to sell existing products, license our technology and obtain third-party funding for new product development efforts. Our future success and ability to achieve and maintain profitability are dependent on the marketing and sales of our IC products into cloud networking, communications, security appliances, monitoring and test, data center, video, and other markets requiring high-bandwidth memory access.

The amount of data and the number of users and devices is growing exponentially, driven primarily by commercial and consumer cloud applications, video services, high speed mobile networks, Internet of Things, or IoT, and many other cloud applications. In order to meet these demands, the new cloud infrastructure; including the backbone, edge, access network and data centers must scale in both speed and intelligence to handle real-time security, bandwidth allocation, and service-level expectations. In addition, workloads or applications delivered at a massive scale from the cloud require flexible, efficient data and computing transmission to optimize resources to enable these applications and lower the overall cost, size and power of the data center. These increased demands strain

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communication between onboard IC devices, limiting the data throughput in network switches and routers and the network backbone.

To meet these demands, carrier and enterprise networks are merging with the cloud and are undergoing significant changes and, most significantly, are migrating to packet-based Ethernet networks that enable higher throughput, lower cost and uniform technology across access, core and metro network infrastructure. These networks are now being designed to deliver voice, video and high-speed Internet services on one converged, efficient and flexible network. These trends require networking systems, especially the high-speed switches and routers that primarily comprise these networks, to comply with evolving market requirements and be capable of providing new services and better quality of service while supporting new protocols and standards. To support these trends, traditional OEM network and telecommunications equipment manufacturers, such as Alcatel-Lucent (a subsidiary of Nokia Corporation), Cisco Systems, Inc., Tel. LM Ericsson, Fujitsu Ltd., Hitachi Ltd., Huawei Technologies, Juniper Networks, Inc., Nokia Corporation, and ZTE Corporation, as well as a new set of white-box solutions from new vendors and cloud-service providers, must offer higher levels of packet forwarding rates, bandwidth density and be optimized to enable higher-density, lower power data path connectivity in the next generations of their networking systems.

Networking communications, security, video and computing systems throughout the cloud network must operate at higher speed and performance levels, and so require new generations of packet processors and improved memory subsystems to enable system performance. These systems and their component line cards generally need to support aggregate rates of 100 gigabits per second, or Gbps, and above to meet the continued growth in network traffic. Cloud services have accelerated this transition with applications such as security. Data centers and access equipment that were previously aggregating slower traffic at rates of 1Gbps to 10Gbps, and 40Gbps, now are being designed to aggregate traffic at 100 Gbps, or more. The transition to 100 Gbps networks is underway, and the increase in data rates for these networks is expected to continue to grow rapidly over the coming years.

Several types of semiconductors are included on each line card, including one or more processors and multiple memory chips. These processors are complex ICs or IC chipsets that perform high-speed data or packet processing for functions, such as traffic routing, shaping, metering, billing, statistics, detection, steering, security, video processing, monitoring and workload acceleration. The line cards use various types of memory ICs to facilitate temporary packet storage and assist in the analysis and tracking of information embedded within the data flowing through the processors. After a packet enters the line card, a packet or data processor helps separate the packet into smaller pieces for rapid analysis. In a typical packet-based network for example, the data is broken up into the packet header, which contains vital information on packet destination and type, such as the Internet protocol address, and the payload, which contains the data being sent. Generally, the line card operations must occur at full data rates and typically require accessing memory ICs many times. Simultaneously, the packet’s payload, which may be substantially larger than the packet header, is also stored in memory ICs until processing is complete and the packet can re-combine and be sent to its next system destination. Within the line card, communication between the packet processor and memory ICs occurs through an interface consisting of combinations of physical pins on each type of chip. These pins are grouped together in a parallel or a serial architecture to form a pathway, called a bus, through which information is transferred from one IC to the next.

Today, the majority of physical buses that connect networking equipment and components use a parallel architecture to communicate between processors and memory ICs, which means information can travel only in one direction and in one instance at a time. As processing speeds increase, the number of pins required and the speed of the bus in a parallel architecture become a limitation on system performance and capability. In contrast, the number of connections is reduced substantially across fewer, higher-rate pins in a serial architecture, and data is transferred simultaneously in both directions. Data transfer rates are limited by the data access rates of the various ICs included on the line card, thus leading to bottlenecks when these ICs perform inadequately. In order to remove these bottlenecks and meet next-generation bandwidth requirements, the line card ICs need to support higher access rates enabled by internal memory or high-speed serial bus architectures and these more advanced interface protocols.

Most networking and communication systems sold and in operation today include line cards that process data at speeds ranging from 10 Gbps, to 100 Gbps, and support many aggregated slower ports. To accommodate the substantial and growing increase in demand for networking communications and applications, networking systems manufacturers are developing and bringing to market next-generation systems that run at aggregate speeds of 100 Gbps to 400 Gbps or more with developments underway to scale to thousands of Gbps, or terabits, per second. However, although processor performance in applications such as computing and networking has continued to double nearly every 18 months, or even

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sooner, the performance of memory technology has generally been able to double only once every 10 years. Existing memory IC solutions based on parallel interface architecture easily support speeds up to 40 Gbps, but are not optimal for meeting speeds of 100 Gbps and beyond due to system-level limitations for pin counts, power and performance. These networking and communications systems are generally comprised of a chassis populated by four to 16 line cards. Often, these systems are shipped to customers with only a portion of the line card slots populated, and the customer will add additional line cards subsequently to increase system performance, capacity and features.

Each line card requires a significant amount of memory to support its processing capabilities. Traditional external memory IC solutions currently used on line cards include both dynamic random access memory, or DRAM, and static random access memory, or SRAM. Line cards in networking systems use both specialized, high-performance DRAM ICs, such as reduced-latency DRAM, or RLDRAM, low-latency DRAM, or LLDRAM, and commodity DRAM, such as double data rate, or DDR ICs. The latest DDR memory called high-bandwidth memory, or HBM, provides high bandwidth, but has fundamentally slow access time. For very high access, networking systems use higher-performance SRAM ICs such as quad data rate, or QDR SRAM. These memories are very fast, but are much smaller, more costly and burn more power than traditional DRAM. Substantially all of these traditional memory IC solutions use parallel interfaces, which are slower than serial interfaces, so we believe they will be increasingly challenged to meet the performance, pin count, area and power requirements as networking systems expand beyond 100 Gbps. The result is a gap between processor and memory performance. To meet the higher performance requirements being demanded by the industry, while using current components and architectural approaches, system designers must add more discrete memory ICs to the line cards and/or add more embedded memory on the packet processor. This results in higher cost and power consumption, the use of more space on the line cards and additional communication interference between the ICs, which in turn results in additional bandwidth limitation problems. We believe our Bandwidth Engine family of products is well suited to address these challenges and replace these traditional memory solutions.

We have developed our ICs to synergistically address the need for high-speed data access and throughput currently confronting system designers. We expect our IC products to meet the increasing demands placed on conventional memory technology used on the line cards in high-speed systems. We believe that our products and technology are well positioned as replacements for existing IC solutions in order to meet the needs of a growing number of data processing applications with aggregate rates greater than 100 Gbps that require high bandwidth and high access rate to memory.

We have leveraged our proprietary intellectual property, or IP, to design our IC products to help networking OEMs address the growing bottlenecks in system performance. We have incorporated critical features into our product families to accomplish this objective.

On-Chip Acceleration

One significant performance bottleneck in any network line card is the need to transfer data between discrete ICs. Many of these data-transfer operations are iterative in nature, requiring subsequent, back-to-back accesses of the memory IC by the processor IC. Our Bandwidth Engine ICs include an arithmetic logic unit, or ALU, which enables the performance of mathematical operations on data. Moving certain processing functions from the processor IC to the Bandwidth Engine IC through the use of this embedded ALU, reduces the number of processing transactions and frees the processor IC to perform other important networking or micro-processing functions.

The PSE takes this concept one step further by incorporating integrated search-optimized processors. The processors can be programmed by the user to offload and accelerate standard and/or customized functions from the main processor thereby reducing memory transactions and data path complexity to provide improved performance and lower system latency.

High-Performance Interface

High-speed, efficient interfaces are critical building blocks to meet high data transfer rate requirements for communication between ICs on network line cards. We believe that current networking system requirements necessitate an industry transition from parallel to serial interface. As a result, semiconductor companies are increasingly turning to serial interface architectures to achieve needed system performance. For example, high-performance ICs that are sold

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into wide markets, such as field programmable gate arrays, or FPGAs, and network processing units, NPUs, are using serial interfaces to ensure they can compete with custom designed application specific ICs, or ASICs, by matching their performance. Using serial interfaces, IC developers also are able to reduce pin count (the wired electrical pins that connect an IC to the network line card on which it is mounted) on the IC. With reducing geometries, the size of most high-performance ICs is dictated by the number of pins required, rather than the amount of logic and memory embedded in the chip. As a result, using serial interface facilitates cost reduction and reduced system power consumption, while improving the performance of both the IC itself and the overall system. While serial interfaces provide significantly enhanced performance over parallel interfaces, SerDes interfaces traditionally have had higher power consumption, which is a challenge for IC designers. Our SerDes interfaces, however, are optimized to meet our customers’ signal integrity, low- power consumption and latency requirements.

We make our interface technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering their development and validation costs. Interoperability reduces development time, thereby reducing the overall time to market of our customers’ systems.

GigaChip Interface Protocol

In addition to the physical characteristics of the serial interface, the protocol used to transmit data is also an important element that impacts speed and performance. To address this and complement our Bandwidth Engine devices, we have developed the GigaChip Interface®, or GCI, which is an open-interface transport protocol optimized for efficient chip-to-chip communications. The GCI electrical interface is compatible with the current industry standard (Common Electrical Interface, release #11, or CEI-11G-SR and XFI) to simplify electrical interoperability between devices. GCI can enable highly efficient serial chip-to-chip communications, and its transport efficiency averages 90% for the data transfers it handles. GCI is included in our ICs and is offered to customers and prospective partners on terms intended to encourage widespread adoption.

High-Performance and High-Density Memory Architecture

The high-density of our proprietary 1T-SRAM technologies stems from the use of a single-transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM, or 6T-SRAM. Embedded memory utilizing our 1T-SRAM technologies typically provides speeds essentially equal to or greater than the speeds of traditional SRAM and DRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than DRAM technology. Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generate less heat than traditional SRAM when operating at the same speed. The 1T-SRAM allows us to integrate more high-performance memory using less expensive processing technology, reduces system level heat dissipation and enables reliable operation using lower-cost packaging.

Our primary business objective is to be a profitable IP-rich fabless semiconductor company offering ICs that deliver unparalleled memory bandwidth and access rate performance for high-performance data processing in cloud networking, security appliances, video, test and monitoring, and data center systems. The key components of our strategic plan include the following strategies:

Target Large and Growing Markets

Our initial strategy is to target the multi-billion dollar networking telecommunications, security appliance and data center OEM equipment markets, and we have developed products to support the growth in 100 Gbps and higher networking speeds. We are currently supporting numerous customers, with whom we have achieved design wins. We continue to actively pursue additional design wins for the use of our ICs in our target markets. We believe our design wins represent the potential for significant future revenue growth. With limited history to date, however, we cannot estimate how much revenue each design win is likely to generate, or how much revenue all of these (and future design wins) are likely to generate. There is no assurance that these customer designs will be shipped in large volume by our customers to their customers, however.

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Expand Adoption of the GigaChip Interface Protocol

We have provided our GCI interface protocol as an open industry standard that may be designed into other ICs in the system, as we believe this will further enable serial communication on network line cards and encourage adoption of our Bandwidth Engine IC products. A number of IC providers and partners have publicly announced their support of GCI and Bandwidth Engine, including the largest FPGA providers, Altera Corporation (a subsidiary of Intel Corporation), Xilinx, Inc., and EZchip Semiconductor Ltd. (a subsidiary of Mellanox Technologies Ltd.), with whom we work closely to support common customers. In addition, multiple networking systems companies, including actual and prospective customers, have adopted GCI.

Build Long-Term Relationships with FPGA Vendors and Suppliers of Data Processing Solutions

We believe that having long-term relationships with FPGA providers is critical to our success, as such relationships enable us to reduce our time-to-market, provide us with a competitive advantage and expand our target markets. A key consideration of network system designers is to demonstrate interoperability between our IC products and the data processing utilized in their systems. To obtain design wins, we must demonstrate this interoperability, and also show that our IC works optimally with the packet processor to achieve the performance requirements. In addition, our current strategy requires packet processor suppliers to adopt our GCI interface. To that end, we have been working closely with FPGA and application specific standard product providers, to enable interoperability between our Bandwidth Engine IC products and their high-performance products. To facilitate the acceptance of our Bandwidth Engine ICs, we have made available development and characterization kits for system designers to evaluate and develop code for next-generation networking systems. Our characterization kits are fully-functional hardware platforms that allow FPGA and ASIC providers, and their customers, to demonstrate interoperability of the Bandwidth Engine IC with the ASIC or FPGA the designers use within their networking systems.

The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element. Our Bandwidth Engine ICs combine: (1) our proprietary high-density, high-speed, low latency embedded memory, (2) our high-speed serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM memory and serial interface with logic and other intelligence functions provides a system-level solution and significantly improves overall system performance at lower cost, size and power consumption. Our Bandwidth Engine ICs can provide up to and over 4.5 billion memory accesses per second, which is more than twice the performance of current memory-based solutions. They also can enable system designers to significantly narrow the gap between processor and memory IC performance. Customers that design Bandwidth Engine ICs onto the line cards in their networking systems will re-architect their systems at the line-card level and use our product to replace traditional memory solutions. When compared with existing commercially available solutions, our Bandwidth Engine ICs may:

· provide up to four times the performance;

· reduce power by approximately 50%;

· reduce cost by greater than 50%; and

· result in a dramatic reduction in IC pin counts on the line card.

Our first-generation Bandwidth Engine IC products contain 576 megabytes, or MB, of memory and use a serial interface with up to 16 lanes operating at up to 10.3 Gbps per lane. We announced the end-of-life of these products and expect to complete fulfillment of last-time customer orders by December 31, 2018.

Our second-generation Bandwidth Engine IC products contain 576 MB of memory and use a SerDes interface with up to 16 lanes operating at up to 15 Gbps per lane. In addition to a speed improvement of up to 50% over our first-generation products, the architecture has enabled multiple family-member parts with added specialized features. We

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have been shipping our Bandwidth Engine 2 IC products since 2013 and expect these products to be our primary revenue source for the foreseeable future.

Our third-generation Bandwidth Engine IC products contain 1152 MB of memory and use a SerDes interface with up to 16 lanes operating at up to 30 Gbps per lane. Bandwidth Engine 3 targets support for packet-processing applications with up to five billion memory single word accesses per second, as well as burst mode to enable full duplex buffering up to 400 Gbps for ingress, egress and oversubscription applications. The devices provide benefits of size, power, pin count and cost savings to our customers. We do not anticipate significant revenues from these products until 2019 or later.

Programmable Search Engine (PSE)

We brought our PSE IC products to market in 2016 to further leverage our proven serial interface technology and high-density integrated memory with the processor engine architecture to enable high-speed customizable search, security, and data analysis functions for networking, security, and data center applications. Our PSE architecture features 32 search-optimized processor engines, data flow schedulers, and over a terabit of internal access bandwidth. The device leverages our GCI technology and high-density integrated memory (1152 Mb of 1T-SRAM embedded memory).

Historically, we have offered our memory and interface technologies on a worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies through product development, technology licensing and joint marketing relationships. We licensed our IP technology to semiconductor companies who incorporated our technology into ICs that they sold to their customers. As a result of the change in our corporate strategy, since early 2012, our IP licensing activities have been limited, and we expect this to continue. Royalty and other revenue generated from our existing IP agreements represented 45% of our total revenue in 2015 and 24% in 2016. However, during 2017, 11% of our total revenues were generated from royalties related to our existing licensing arrangements, as we continue to collect royalties from 1T-SRAM licensees. Licensing and royalty revenues have been declining since 2010, and we expect continued decline of royalty revenues in 2018.

Our ability to compete in the future depends on successfully improving our technology to meet the market’s increasing demand for higher performance and lower cost requirements. Development of our IC products requires specialized chip design and product engineers, as well as significant fabrication and testing costs, including mask costs, as we bring these products to market. During 2017, we substantially reduced our headcount, and have limited internal resources available for new IC product development, which will result in fewer product improvements and new developments. In the near term, our planned product roadmap will include software-based capabilities and features that leverage our existing base of IC products.

We believe that systems OEMs typically prefer to extend the use of traditional memory solutions and their parallel interfaces, despite performance and costs challenges, and are reluctant to change their technology platforms and adopt new designs and technologies, such as serial interfaces, which are an integral part of our product solutions. Therefore, our principal selling and marketing activities to date have been focused on persuading these OEMs and key component specialists that our solutions provide critical performance advantages, as well as on securing design wins with them.

In addition to our direct sales personnel, we sell through sales representatives and distributors in the United States and Asia. We also have applications engineers who support our customer engagements and engage with the customers’ system architects and designers to propose and implement our IC and IP solutions, such as the GCI Interface, to address their systems challenges.

In the markets we serve, the time from initial customer engagement to design win to production volume shipments can range from 18 to 36 months. Networking, communications and security appliance systems can have a product life from a few years to over 10 years once a product like ours has been designed into the system.

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Our revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue. For the year ended December 31, 2017, Flextronics, which primarily purchases on behalf of Palo Alto Networks, Inc. and Nokia, formerly Alcatel-Lucent, Clavis Company, formerly Kogent, our Japanese IC distributor and Nokia, represented 46%, 17% and 11% of total revenue, respectively. For the year ended December 31, 2016, Alcatel-Lucent, Clavis Company and Taiwan Semiconductor Manufacturing Co., Ltd., or TSMC, represented 47%, 21% and 13% of total revenue, respectively. For the year ended December 31, 2015, Alcatel-Lucent, TSMC and Clavis Company represented 34%, 31% and 12% of total revenue, respectively.

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success, and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of December 31, 2017, we held 69 U.S. and 42 foreign patents on various aspects of our technology, with expiration dates ranging from 2018 to 2035. We also held 11 pending patent applications in the U.S. and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

In December 2011, we sold 43 United States and 30 related foreign memory technology patents for $35 million in cash pursuant to a patent purchase agreement. Under the agreement, we retained a license to all of the sold patents that is unlimited with respect to our development, manufacturing and distribution of our Bandwidth Engine IC product line and any other proprietary products that we develop, as long as they are not DRAM ICs. We also retained the rights necessary to renew existing 1T-SRAM licenses and to grant licenses similar in scope to identified foundries. We also retained rights to grant licenses for our second source purposes, to enable certain kinds of technology development and, to a limited extent, for certain ASIC products that incorporate one of our technology macros. However, the patent purchase agreement limits our rights to grant licenses under the sold patents outside the scope of our retained license, and, in particular, limits the number of future licenses of 1T-SRAM memory technology that we can grant to developers of systems-on-chips, which used to be the principal focus of our 1T-SRAM licensing activities.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, “Risk Factors.”

The markets for our products are highly competitive. We believe that the principal competitive factors are:

· processing speed and performance;

· density and cost;

· power consumption;

· reliability;

· interface requirements;

· ease with which technology can be customized for and incorporated into customers’ products; and

· level of technical support provided.

We believe that our products compete favorably with respect to each of these criteria. Our proprietary 1T-SRAM embedded memory and high-speed serial interface IP can provide our Bandwidth Engine ICs with a competitive advantage over alternative devices. Alternative solutions are either DRAM or SRAM-based and can support either the memory size or speed requirements of high-performance networking systems, but generally not both. DRAM solutions provide a significant amount of memory at competitive cost, but DRAM solutions do not have the required fast access and cycle times to enable high-performance. The DRAM solutions currently used in networking systems include RLDRAM from Micron Technology, Inc., or Micron, and Integrated Silicon Solutions, Inc., LLDRAM from Renesas, DDR from Samsung Electronics Co., Ltd., Micron and others, and HBM, which is stacked memory from Samsung

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Electronics Co. and SK Hynix. SRAM solutions can meet high-speed performance requirements, but often lack adequate memory size. The SRAM solutions currently used in networking systems primarily include QDR or similar SRAM products from Cypress Semiconductor Corporation and GSI Technology, Inc. Most of the currently available SRAM and DRAM solutions use a parallel, rather than a serial interface. To offset these drawbacks, system designers generally must use more discrete memory ICs, resulting in higher power consumption and greater utilization of space on the line card.

Our competitors include established semiconductor companies with significantly longer operating histories, greater name recognition and reputation, large customer bases, dedicated manufacturing facilities and greater financial, technical, sales and marketing resources. This may allow them to respond more quickly than us to new or emerging technologies or changes in customer requirements. Generally, customers prefer suppliers with greater financial resources than we have currently. Many of our competitors also have significant influence in the semiconductor industry. They may be able to introduce new technologies or devote greater resources to the development, marketing and sales of their products than we can. Furthermore, in the event of a manufacturing capacity shortage, these competitors may be able to manufacture products when we are unable to do so.

Our Bandwidth Engine ICs compete with embedded memory solutions, stand-alone memory ICs, including both DRAM and SRAM ICs, and ASICs designed by customers in-house to meet their system requirements. Our prospective customers may be unwilling to adopt and design-in our ICs due to the uncertainties and risks surrounding designing a new IC into their systems and relying on a supplier that has limited history of manufacturing such ICs and limited financial resources. In addition, Bandwidth Engine ICs require the customer and its other IC suppliers to implement our chip-to-chip communication protocol, the GCI interface. These parties may be unwilling to do this if they believe it could adversely impact their own future product developments or competitive advantages, or, if they believe it might complicate their development process or increase the cost of their products. To remain competitive, we believe we must provide unparalleled memory IC solutions with the highest bandwidth capability for our target markets, which solutions are engineered and built for high-reliability carrier and enterprise applications.

We depend on third-party vendors to manufacture, package, assemble and test our IC products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility for boards and system assembly. By outsourcing manufacturing, we can avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

We perform an ongoing review of product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meets design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers. We have achieved ISO 9001:2008 certification, and all of our manufacturing vendors have also achieved ISO 9001 certification.

As of December 31, 2017, we had 24 employees all of whom are located in the United States, consisting of 14 in research and development and manufacturing operations and 10 in sales, general and administrative functions.

We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934, as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read and obtain copies of any materials we file with the SEC at the SEC’s Public Reference Room at 450 Fifth Street, NW, Washington, DC 20549. You can obtain additional information about the operation of the Public Reference Room by calling the SEC at 1.800.SEC.0330. In addition, the SEC maintains a website (www.sec.gov) that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

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MoSys, Inc., together with its subsidiaries (“MoSys,” the “Company,” “we,” “our” or “us”), is a fabless semiconductor company focused on the development and sale of integrated circuits, or ICs, for the high-speed networking, communications, storage and computing markets. Our solutions deliver time-to-market, performance, signal integrity, power, area and economic benefits for system original equipment manufacturers, or OEMs. We have developed two IC product lines under the Bandwidth Engine and LineSpeed product names. Bandwidth Engine ICs integrate our proprietary 1T-SRAM high-density embedded memory with our integrated macro function technology and a highly efficient serial interface protocol resulting in a monolithic memory IC solution optimized for transaction performance. As the bandwidth requirements and amount of processing per packet increase in high-speed networking systems, critical memory access bottlenecks occur. Our Bandwidth Engine IC, with its combination of serial I/O, high-speed memory, offload functions and efficient, intelligent access, drastically increases memory accesses per second, removing these bottlenecks. In addition, the serial interface and high memory capacity reduce the board footprint, number of pins and complexity while using less power. The LineSpeed IC product line, which we announced in March 2013, is comprised of non-memory, high-speed serialization-deserialization, or SerDes, I/O physical layer, or PHY, devices that ensure signal integrity between interfaces which is commonly referred to as clock data recovery, or CDR, or retimer functionality, which perform multiplexing to transition from one speed to another, commonly referred to as Gearbox functionality. These PHY devices reside within optical modules and networking equipment line cards designed for next-generation Ethernet and optical transport network applications.

We are currently supporting existing design win customers, primarily for Bandwidth Engine, and actively pursuing additional design wins for the use of our ICs in networking, communications and data center equipment. We have established initial pricing of our IC products ordered to date, but longer-term volume prices will be subject to negotiations with our customers and may vary substantially from these initial prices.

Prior to 2010, our primary business was the design, development, marketing, sale and support of differentiated intellectual property, or IP, including embedded memory and high-speed parallel and serial I/O used in advanced systems-on-chips, or SoCs. Currently, we are focused on developing differentiated IP-rich IC products and are dedicating all our research and development, marketing and sales budgets to these IC products. Royalty and other revenue generated from our existing IP agreements represented 45% of our total revenue in 2015 and 24% in 2016. We expect royalty and other revenue to continue to decline in 2017 both in absolute dollars and as a percentage of revenues.

Our future success and ability to achieve and maintain profitability are dependent on the marketing and sales of our IC products into networking, communications and other markets. Since the beginning of 2010, we have invested substantially all of our of our research and development resources toward development of our ICs, and, as of the end of 2012, had ceased our efforts to actively market our IP and establish license agreements for customers’ new SoC development projects.

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The amount of data being transferred by networking, storage and computing systems is increasing rapidly, primarily driven by the growth of the Internet and demand for real-time processing of bandwidth intensive applications, such as video-on-demand, Internet protocol TV, peer-to-peer and cloud computing, web2.0 applications, 4G/LTE wireless, voice-over-Internet protocol, and many others. In order to meet these demands, the network backbone, access, storage and data center infrastructure must scale in bandwidth and processing capability. In addition, system designers face the challenge of increasing the throughput of all subsystems for a variety of applications, such as video games, medical record and imaging transfers, and file sharing. These increased demands strain communication between onboard IC devices, limiting the data throughput in network switches and routers and the network backbone.

To meet these demands, carrier and enterprise networks are undergoing significant changes and, most significantly, are migrating to packet-based Ethernet networks that enable higher throughput, lower cost and uniform technology across access, core and metro network infrastructure. These networks are now being designed to deliver voice, video and high-speed Internet access on one converged, efficient and flexible network. These trends require networking systems, especially the high-speed switches and routers that primarily comprise these networks, to comply with evolving market requirements and be capable of providing new services and better quality of service while supporting new protocols and standards. To support these trends, OEM network and telecommunications equipment manufacturers, such as Alcatel-Lucent (a subsidiary of Nokia Corporation), Brocade Communications Systems, Inc., Cisco Systems, Inc., Tel. LM Ericsson, Fujitsu Ltd., Hitachi Ltd., Huawei Technologies, Juniper Networks, Inc., Nokia Corporation, and ZTE Corporation, must offer higher levels of packet forwarding rates, bandwidth density and be optimized to enable higher-density, lower power data path connectivity in the next generations of their networking systems.

Networking and telecommunications systems throughout the network must operate at higher speed and performance levels and so require new generations of packet processors and improved memory subsystems, as well as new physical interface products, to enable system performance. These systems and their component line cards generally need to support aggregate rates of 100 gigabits per second, or Gbps, and above to meet the continued growth in network traffic. Cloud services have accelerated this transition with applications such as security. Data centers and access equipment that were previously aggregating slower traffic such at 1Gbps to 10Gbps, and 40Gbps, now are being designed to aggregate traffic at 10Gbps to 100Gbps, or more. The transition to 100 Gbps networks has begun, and 100 Gbps networks are expected to grow rapidly over the coming years.

Several types of semiconductors are included on each line card, including PHY, one or more packet processors and multiple memory chips. Packet processors are complex ICs or IC chipsets that perform high speed processing for functions, such as traffic routing, shaping, metering, billing, statistics, detection and steering. The line cards use various types of memory ICs to facilitate temporary packet storage and assist in the analysis and tracking of information embedded within each packet flowing through the processors. After a packet enters the line card through a PHY, a packet or data processor helps separate the packet into smaller pieces for rapid analysis. Typically, the data is broken up into the packet header, which contains vital information on packet destination and type, such as the Internet protocol address, and the payload, which contains the data being sent. Generally, the line card operations must occur at full data rates and typically require accessing memory ICs many times. Simultaneously, the packet’s payload, which may be substantially larger than the packet header, is also stored in memory ICs until processing is complete and the packet can re-combine and be sent to its next system destination. Within the line card, communication between the packet processor and memory ICs occurs through an interface consisting of combinations of physical pins on each type of chip. These pins are grouped together in a parallel or a serial architecture to form a pathway, called a bus, through which information is transferred from one IC to the next.

Today, the majority of physical buses that connect networking equipment and components use a parallel architecture to communicate between processors and memory ICs, which means information can travel only in one direction and in one instance at a time. As processing speeds increase, the number of pins required and the speed of the bus in a parallel architecture become a limitation on system performance and capability. In contrast, the number of connections is reduced substantially across fewer, higher-rate pins in a serial architecture, and data is transferred simultaneously in both directions. Data transfer rates with high-speed serial bus architectures and more advanced I/O protocols are limited by the capabilities of the various ICs included on the line card, thus leading to bottlenecks when these ICs perform inadequately. In order to remove these bottlenecks and meet next-generation bandwidth requirements, the line card ICs must support high-speed serial bus architectures and these more advanced I/O protocols.

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Most networking and communication systems sold and in operation today include line cards that process data at speeds ranging from 10 Gbps, to 100 Gbps, and support many aggregated slower ports. To accommodate the substantial and growing increase in demand for networking communications and applications, networking systems manufacturers are developing and bringing to market next-generation systems that run at aggregate speeds of 100 to 400 Gbps or more with developments underway to scale to thousands of Gbps, or terabits, per second. However, although processor performance in applications such as computing and networking has continued to double nearly every 18 months, or even sooner, the performance of memory technology has generally been able to double only once every 10 years. Existing memory IC solutions based on parallel I/O architecture easily support speeds up to 40 Gbps, but are not optimal for meeting speeds of 100 Gbps and beyond due to system-level limitations for pin counts, power and performance. These networking and communications systems are generally comprised of a chassis populated by four to 16 line cards. Often, these systems are shipped to customers with only a portion of the line card slots populated, and the customer will add additional line cards subsequently to increase system performance and capacity.

Each line card requires a significant amount of memory to support its processing capabilities. Traditional external memory IC solutions currently used on line cards include both dynamic random access memory, or DRAM, and static random access memory, or SRAM. Line cards in networking systems use both specialized, high-performance DRAM ICs, such as reduced-latency DRAM, or RLDRAM, low-latency DRAM, or LLDRAM, and commodity DRAM, such as double data rate, or DDR ICs. In addition, networking systems use higher-performance SRAM ICs such as quad data rate, or QDR SRAM. Substantially all of these traditional memory IC solutions use parallel interfaces, which are slower than serial interfaces, so we believe they will be increasingly challenged to meet the performance, pin count, area and power requirements as networking systems expand beyond 100 Gbps. The result is a gap between processor and memory performance. To meet the higher performance requirements being demanded by the industry, while using current components and architectural approaches, system designers must add more discrete memory ICs to the line cards and/or add more embedded memory on the packet processor. This results in higher cost and power consumption, the use of more space on the line cards and additional communication interference between the ICs, which in turn results in additional bandwidth limitation problems. We believe our Bandwidth Engine family of products is well suited to address these challenges and replace these traditional memory solutions.

In addition, each line card requires PHY products to provide interoperability and signal integrity functions. As network speeds increase beyond 100Gbps, the serial data rates are transitioning from 10Gbps to 25Gbps. This means that the signal integrity challenges (maintaining the quality of the electrical signals) of moving these high speed signals around within line cards, or between line cards and systems using fiber optic or copper cable, increase as data rates increase. These networking systems often use copper or optical modules to modify signals for transmission over longer distances ranging from tens of meters to thousands of kilometers. Optical modules convert electrical signals to optical signals for transportation over longer distances from one system to another system. Because of the challenges arising from the increase in network speeds, new 100Gbps standards have emerged that specify a CDR or retimed interface on optical modules, which was not the case at 10Gbps based interfaces. Each 100Gbps module and above using 25Gbps per lane will require a CDR/retimer function inside the module to meet these requirements. In addition, the systems themselves also require additional support to move signals between the module and the system, and these challenges become more acute as the distance increases. Our LineSpeed products address these new line card and optical module challenges by providing unique signal integrity and feature sets that align with the industry standards, as well as provide backward compatibility for the previous data rates. We believe our LineSpeed PHY products are well suited ensure the quality of signals and/or increase the transmission distance for both short reach (e.g., between ICs on a line card) or long-reach (e.g., between line cards or systems).

We have developed our Bandwidth Engine and LineSpeed families of ICs to synergistically address the need for high-speed data access and throughput currently confronting networking system designers. We expect our IC products to meet the increasing demands placed on conventional memory technology used on the line cards in high-bandwidth networking systems. We believe that our products and technology are well positioned as replacements for existing IC solutions in order to meet the needs of the next-generation networking systems that will require a large number of packet lookups and to support aggregated rates greater than 100 Gbps.

Our historical business was focused on the licensing of our proprietary 1T- SRAM and SerDes I/O technologies. We have leveraged our proprietary IP to design our Bandwidth Engine and LineSpeed IC product families

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to help networking OEMs address the growing bottlenecks in system performance. We have incorporated critical features into our product families to accomplish this objective.

On-Chip Functionality

One significant performance bottleneck in any network line card is the need to transfer data between discrete ICs. Many of these data-transfer operations are iterative in nature, requiring subsequent, back-to-back accesses of the memory IC by the processor IC. Our Bandwidth Engine ICs include an arithmetic logic unit, or ALU, which enables the Bandwidth Engine IC to perform mathematical operations on data. Moving certain processing functions from the processor IC to the Bandwidth Engine IC through the use of this embedded ALU, reduces the number of I/O transactions and frees the processor IC to perform other important networking or micro-processing functions.

High-Performance Interface

High-speed, efficient interface I/Os are critical building blocks to meet high data transfer rate requirements for communication between ICs on network line cards. We believe that current networking system requirements necessitate an industry transition from parallel to serial I/O. As a result, semiconductor companies are increasingly turning to serial I/O architectures to achieve needed system performance. For example, high-performance ICs that are sold into wide markets, such as field programmable gate arrays, or FPGAs, and network processing units, NPUs, are using serial I/Os to ensure they can compete with custom designed application specific ICs, or ASICs, by matching their performance. Using serial I/O, IC developers also are able to reduce pin count (the wired electrical pins that connect an IC to the network line card on which it is mounted) on the IC. With reducing geometries, the size of most high-performance ICs is dictated by the number of pins required, rather than the amount of logic and memory embedded in the chip. As a result, using serial I/O facilitates cost reduction and reduced system power consumption, while improving the performance of both the IC itself and the overall system. While SerDes I/Os provide significantly enhanced performance over parallel I/Os, SerDes I/Os traditionally have had higher power consumption, which is a challenge for IC designers. Our SerDes I/Os, however, are tuned for low power consumption to meet our customers’ stringent power consumption requirements.

We make our I/O technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering their development and validation costs. Interoperability reduces development time, thereby reducing the overall time to market of our customers’ systems.

Analog Design Capabilities

We have invested in personnel needed to define, design and market high- performance analog IC products. We have built a team of experienced engineers who combine industry expertise with advanced semiconductor design expertise to meet customer requirements and develop new products to bring to market. We initially developed our team of analog engineers to develop the SerDes I/O used in our Bandwidth Engine families of products. We leveraged the capabilities of this team to produce our LineSpeed IC products, which are primarily comprised of analog circuitry.

GigaChip Interface Protocol

In addition to the physical characteristics of the serial I/O, the protocol used to transmit data is also an important element that impacts speed and performance. To address this and complement our Bandwidth Engine devices, we have developed the GigaChip Interface®, or GCI, which is an open-interface transport protocol optimized for efficient chip-to-chip communications. The GCI electrical interface is compatible with the current industry standard (Common Electrical Interface, release #11, or CEI-11G-SR and XFI) to simplify electrical interoperability between devices. GCI can enable highly efficient serial chip-to-chip communications, and its transport efficiency averages 90% for the data transfers it handles. GCI is included in our Bandwidth Engine ICs, and is offered to customers and prospective partners on terms intended to encourage widespread adoption.

High-Performance and High-Density Memory Architecture

The high-density of our proprietary 1T-SRAM technologies stems from the use of a single-transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM, or 6T-

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SRAM. Embedded memory utilizing our 1T-SRAM technologies typically provides speeds essentially equal to or greater than the speeds of traditional SRAM and DRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than embedded 6T-SRAM technology. Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generate less heat than traditional SRAM when operating at the same speed. This reduces system level heat dissipation and enables reliable operation using lower cost packaging.

Our primary business objective is to be an IP-rich fabless semiconductor company offering ICs that deliver unparalleled memory bandwidth performance for packet processing and improved signal integrity performance for networking, security and data center systems. The key components of the expansion of our strategic plan to become an IC supplier include the following strategies:

Target Large and Growing Markets

Our initial strategy is to target the multi-billion dollar networking telecommunications, security and data center OEM equipment markets, and we have developed products to support the growth in 100 Gbps and higher networking speeds. We are currently supporting approximately 25 existing customers, with whom we have achieved over 85 design wins, which reflects broadening acceptance of our products. We define a design win as the point at which a customer has made a commitment to build a board against the fixed schematic for his system, and this board will utilize our IC products. We continue to actively pursue additional design wins for the use of our ICs in our target markets. We believe our design wins represent the potential for significant future revenues. With limited history to date, however, we cannot estimate how much revenue each design win is likely to generate, or how much revenue all of these (and future design wins) are likely to generate. For example, our first design wins from 2012 and 2013 are starting to ramp into production, and, while we cannot predict how steep these ramps might be, we expect our revenues from them to grow in successive periods over the next few years. There is no assurance that these customer designs will be shipped in large volume by our customers to their customers, however.

Leverage Technologies to Create New Products

Our strategy is to combine our proprietary IP and design and applications expertise to address the needs of several upcoming generations of advanced networking systems. We believe an IC combining our 1T-SRAM and serial I/O with logic, such as in an ALU, and other functions can provide a system-level solution and significantly improve overall system performance at lower cost while using less power. We also seek to leverage our high-speed serial I/O to create non-memory denominated ICs, such as our LineSpeed products. Our initial LineSpeed products targeted the line card and the same customers as our Bandwidth Engine products. This has given us the opportunity to provide both memory and PHY solutions during the sale process. In 2013, we introduced our first LineSpeed products to address the requirements new industry standards were placing on optical modules, as well as line cards.

Expand Adoption of the GigaChip Interface Protocol

We have provided our GCI interface protocol as an open industry standard that may be designed into other ICs in the system, as we believe this will further enable serial communication on network line cards and encourage adoption of our Bandwidth Engine IC products. A number of IC providers and partners have publicly announced their support of GCI and Bandwidth Engine, including the largest FPGA providers, Altera Corporation (a subsidiary of Intel Corporation), Xilinx, Inc., and EZchip Semiconductor Ltd. (a subsidiary of Mellanox Technologies Ltd.), with whom we work closely to support common customers. In addition, multiple networking systems companies, including actual and prospective customers, have adopted GCI.

Build Long-Term Relationships with Suppliers of Packet Processors

We believe that having long-term relationships with packet processor providers is critical to our success, as such relationships may enable us to reduce our time-to-market, provide us with a competitive advantage and expand our target markets. A key consideration of network system designers is to demonstrate interoperability between our Bandwidth Engine IC and the packet processors utilized in their systems. To obtain design wins for our Bandwidth Engine IC, we must demonstrate this interoperability, and also show that our IC works optimally with the packet

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processor to achieve the performance requirements. In addition, our current strategy requires packet processor suppliers to adopt our GCI interface. To that end, we have been working closely with FPGA, ASIC and NPU providers, to enable interoperability between our Bandwidth Engine IC products and their high-performance products. To facilitate the acceptance of our Bandwidth Engine ICs, we have made available development and characterization kits for system designers to evaluate and develop code for next-generation networking systems. Our characterization kits are fully-functional hardware platforms that allow FPGA and ASIC providers, and their customers, to demonstrate interoperability of the Bandwidth Engine IC with the ASIC or FPGA the designers use within their networking systems. Our recent announcement of the third-generation Bandwidth Engine Z30 device, designed for interoperability with the EZ-chip NPS-400, is an example and direct result of this strategy.

Bandwidth Engine

The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element. Our Bandwidth Engine ICs combine: (1) our proprietary high-density, high-speed, low latency embedded memory, (2) our high-speed serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM memory and serial I/O with logic and other intelligence functions provides a system-level solution and significantly improves overall system performance at lower cost, size and power consumption. Our Bandwidth Engine ICs can provide up to and over 4.5 billion memory accesses per second, which is more than twice the performance of current memory-based solutions. They also can enable system designers to significantly narrow the gap between processor and memory IC performance. Customers that design Bandwidth Engine ICs onto the line cards in their networking systems will re-architect their systems at the line-card level and use our product to replace traditional memory solutions. When compared with existing commercially available solutions, our Bandwidth Engine ICs may:

· provide up to four times the performance;

· reduce power by approximately 50%;

· reduce cost by greater than 50%; and

· result in a dramatic reduction in IC pin counts on the line card.

Our first generation Bandwidth Engine IC products contain 576 megabytes, or MB, of memory and use a serial I/O with up to 16 lanes operating at up to 10.3 Gbps per lane. Variations of this IC can have up to two interface ports, with up to eight serial receiver and eight serial transmitter lanes per port for a total of 16 lanes of 10.3 Gbps SerDes interface. These ICs include an ALU, which can perform read-modify-write operations. We have been shipping our initial Bandwidth Engine products since 2012.

Our second generation Bandwidth Engine IC products contain 576 MB of memory and use serial I/O with up to 16 lanes operating at up to 15 Gbps per lane. In addition to a speed improvement of up to 50%, the architecture will enable several family member parts with added specialized features. To date, we have announced three unique devices in this product family:

· MSR620 with burst features optimized for oversubscription buffer applications;

· MSR720 with a write cache and memory coherency capability that allows for deterministic look-ups optimized for state and queue type applications; and

· MSR820 with increased intelligence for lookup, metering and statistics applications by adding dual counters, atomic and extensive metering functions.

We have been shipping our Bandwidth Engine 2 IC products since 2013.

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Our third generation Bandwidth Engine IC products contain 1152 MB of memory and use serial I/O with up to 16 lanes operating at up to 30 Gbps per lane. Bandwidth Engine 3 targets support for packet-processing applications with up to five billion memory single word accesses per second, as well as burst mode to enable full duplex buffering up to 400Gbps for ingress, egress and oversubscription applications. To date, we have announced three unique devices in this product family:

· MSR630 enables high rate lookup or high-performance buffer capabilities; and

· MSR830 offers additional offload capabilities for functions such as statistics and metering to increase performance and add features for next-generation networking and communications equipment; and

· MSRZ30 builds upon the capabilities and performance of the MSR830, with data rates, interface protocol and data structures that are optimized for the EZchip NPS-400 network processing unit, or NPU, and can increase memory bandwidth by up to 50%.

We commenced sampling of these products in the first quarter of 2016.

The devices provide benefits of size, power, pin count and cost savings to our customers. We do not anticipate significant revenues from these products until 2018 or later.

Programmable Search Engine

We brought our Programmable Search Engine, or PSE, IC products to market in early 2016 to further leverage our proven serial interface technology and high-density integrated memory with the processor engine architecture to enable high-speed customizable search, security, and data analysis functions for networking, security, and data center applications. Our PSE architecture features 32 search-optimized processor engines, data flow schedulers, and over a terabit of internal access bandwidth. The device leverages our GCI technology and high-density integrated memory (1152 Mb of 1T-SRAM® embedded memory). The PSE device’s 32 processor elements have direct access to integrated table memory through an internal interconnect and scheduler architecture.

LineSpeed

Our first generation LineSpeed products consist of single-chip PHY ICs, including a 100G multi-mode gearbox and a 100G quad retimer. These devices are designed to support 10, 40 and 100Gbps standards for high-density line cards or modules for next generation ethernet and optical transport network applications. These devices are capable of supporting both short and long reach connections across different specifications. We have developed these PHY ICs to provide the CDR function and to provide signal conversion from lower rates to higher rates both on the line card and within the optical module. We have defined performance and form factor (sizes) for specific devices for optimization of features and performance to solve space challenges both on the line card and in the optical module. We introduced and began sampling these devices in 2013.

Our second generation of LineSpeed products consists of our 100G low power retimer, which is optimized for ultra low power consumption, integrated test features and small size. The low-power retimer is primarily targeting opportunities in 100G CFP2, CFP4 and QSFP28 optical modules and active copper cables. We introduced and began sampling this product in 2014.

Our third generation of LineSpeed products, the Flex family of 100G PHYs, is designed to support the latest industry standards and includes gearbox, Multi-Link Gearbox, or MLG, and high density CDR/retimer devices designed to enable existing and next generation Ethernet and OTN line card applications to support the latest high-density electrical and optical interfaces. To date, we have announced four unique devices in this product family:

· MSH320, a 100Gbps Gearbox with RS-FEC: For adapting 10x10 to 4x25 from 100Gbps optical standards to a host ASIC, MAC/Framer, NPU or FPGA with 10x10G interfaces. The MSH320 includes an integrated Reed-Solomon forward error correction, or RS-FEC, option to enable systems to also support new electrical and optical standards. The device also includes a 10x10Gbps retimer to allow seamless support of 10 and 40Gbps interfaces;

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· MSH225, a 10 Lane Full-Duplex Retimer: For high-density retiming applications where the line rates may be up to 28Gbps per lane and connect to host ASIC, framer, NPU or FPGA ICs equipped with 25Gbps interfaces. Each one of the 20 total independent lanes can be configured to support 10, 25, 40 or 100Gbps standards. The MSH225 integrates optional 100Gbps RS-FEC capability and includes a unique redundant link mode feature to support redundancy, scaling or monitoring features;

· MSH322, a 100Gbps Multi-Link Gearbox for Line Cards for support of high-density, independent 10GE and 40GE interfaces multiplexed into a 100GE (4x25Gbps) host interface, while supporting the latest optical industry standards. The device enables line cards with high-density switches based on 25Gbps interfaces to support two times the density of 10 and 40Gbps ports; and

· MSH321, a derivative Multi-Link Gearbox built into a highly compact package and optimized layout to support the MLG function in module and compact daughter card applications.

While we have a robust pipeline of design win opportunities, to date, less than 10% of our design wins claimed are for our LineSpeed products, and we expect these customers to take a minimum of 12 to 18 months to commence production.

Historically, we have offered our memory and I/O technologies on a worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies through product development, technology licensing and joint marketing relationships. We licensed our IP technology to semiconductor companies who incorporated our technology into ICs that they sold to their customers. As a result of the change in our corporate strategy, since early 2012, our IP licensing activities have been limited, and we expect this to continue. However, during 2016, 24% of our total revenues were generated from royalties related to our existing licensing arrangements, as we continue to collect royalties from 1T-SRAM licensees. Licensing and royalty revenues have been declining since 2010, and we expect continued decline in 2017.

Our ability to compete in the future depends on successfully improving our technology to meet the market’s increasing demand for higher performance and lower cost requirements. We have assembled a team of highly skilled engineers whose activities are focused on developing higher density, higher bandwidth, higher speed and lower cost next generation IC products. Development of our IC products requires specialized chip design and product engineers, as well as significant fabrication and testing costs, including mask costs, as we bring these products to market. We expect our significant future research and development activities to include:

· designing next generation ICs with larger memory blocks and higher-speed SerDes;

· developing versions of our Bandwidth Engine ICs with alternative features, such as lower-speed SerDes, increased chip-level intelligence or smaller memory blocks to allow us to serve a broader range of applications and system requirements;

· developing derivative versions of our LineSpeed ICs to meet customer demands; and

· developing new products that can leverage our proprietary IP portfolio and expand our market opportunity.

No development efforts are being dedicated to creating new or enhanced technology solely for use in licensing offerings.

We believe that networking and communications systems OEMs typically prefer to extend the use of traditional memory solutions and their parallel interfaces, despite performance and costs challenges and are reluctant to change their technology platforms and adopt new designs and technologies, such as serial interfaces, which are an integral part of our

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product solutions. Therefore, our principal selling and marketing activities to date have been focused on persuading these OEMs and key component specialists that our solutions provide critical performance advantages, as well as on securing design wins with them.

Our sales and marketing personnel are located in the United States, Japan and China. In addition to our direct sales team, we sell through sales representatives and distributors in the United States and Asia. We also have multiple applications engineers who support our customer engagements and work closely with our engineering team on product definition. For our products, our applications engineers must engage with the customers’ system architects and designers to propose our IC and IP solutions such as the GCI Interface, to address their systems challenges.

In the markets we serve, the time from initial customer engagement to design win to production volume shipments can range from 18-36 months. Networking and communications systems can have a product life from a few years to over 10 years once a product like ours has been designed into the system.

Our revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue. For the year ended December 31, 2016, Alcatel-Lucent, Kogent, Inc., our Japanese IC distributor and Taiwan Semiconductor Manufacturing Co., Ltd., or TSMC, represented 47%, 21% and 13% of total revenue, respectively. For the year ended December 31, 2015, Alcatel-Lucent, TSMC and Kogent, Inc. represented 34%, 31% and 12% of total revenue, respectively. For the year ended December 31, 2014, TSMC, Kogent, Inc. and Broadcom Ltd. represented 34%, 31% and 11% of total revenue, respectively.

Customers in North America accounted for 63%, 51% and 28% of our revenues for the years ended December 31, 2016, 2015 and 2014, respectively. Customers in Japan accounted for 22%, 15% and 36% of our revenues for the years ended December 31, 2016, 2015 and 2014, respectively. Customers in Taiwan accounted for 13%, 32% and 35% of our revenues for the years ended December 31, 2016, 2015 and 2014, respectively. Our remaining revenues were primarily from customers in the rest of Asia and in Europe.

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success, and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of December 31, 2016, we held 67 U.S. and 36 foreign patents on various aspects of our technology, with expiration dates ranging from 2018 to 2035. We also held 18 pending patent applications in the U.S. and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

In December 2011, we sold 43 United States and 30 related foreign memory technology patents for $35 million in cash pursuant to a patent purchase agreement. Under the agreement, we retained a license to all of the sold patents that is unlimited with respect to our development, manufacturing and distribution of our Bandwidth Engine IC product line and any other proprietary products that we develop as long as they are not DRAM ICs. We also retained the rights necessary to renew existing 1T-SRAM licenses and to grant licenses similar in scope to identified foundries. We also retained rights to grant licenses for our second source purposes, to enable certain kinds of technology development and, to a limited extent, for certain ASIC products that incorporate one of our technology macros. However, the patent purchase agreement limits our rights to grant licenses under the sold patents outside the scope of our retained license and, in particular, limits the number of future licenses of 1T-SRAM memory technology that we can grant to developers of SoCs, which used to be the principal focus of our 1T-SRAM licensing activities.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, “Risk Factors.”

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The markets for our products are highly competitive. We believe that the principal competitive factors are:

· processing speed and performance;

· density and cost;

· power consumption;

· reliability;

· interface requirements;

· ease with which technology can be customized for and incorporated into customers’ products; and

· level of technical support provided.

We believe that our products compete favorably with respect to each of these criteria. Our proprietary 1T-SRAM embedded memory and high-speed serial I/O IP can provide our Bandwidth Engine ICs with a competitive advantage over alternative devices. Alternative solutions are either DRAM or SRAM-based and can support either the memory size or speed requirements of high-performance networking systems, but generally not both. DRAM solutions provide a significant amount of memory at competitive cost, but DRAM solutions do not have the required fast access and cycle times to enable high-performance. The DRAM solutions currently used in networking systems include RLDRAM from Micron Technology, Inc., or Micron, and Integrated Silicon Solutions, Inc., LLDRAM from Renesas and DDR from Samsung Electronics Co., Ltd., Micron and others. In addition, Micron has a hybrid memory cube DRAM product, which consists of multiple DRAMs connected with a serial interface. SRAM solutions can meet high-speed performance requirements, but often lack adequate memory size. The SRAM solutions currently used in networking systems primarily include QDR or similar SRAM products from Cypress Semiconductor Corporation and GSI Technology, Inc. The majority of the currently available SRAM and DRAM solutions use a parallel, rather than a serial I/O. To offset these drawbacks, system designers generally must use more discrete memory ICs, resulting in higher power consumption and greater utilization of space on the line card.

Our competitors include established semiconductor companies with significantly longer operating histories, greater name recognition and reputation, large customer bases, dedicated manufacturing facilities and greater financial, technical, sales and marketing resources. This may allow them to respond more quickly than us to new or emerging technologies or changes in customer requirements. Many of our competitors also have significant influence in the semiconductor industry. They may be able to introduce new technologies or devote greater resources to the development, marketing and sales of their products than we can. Furthermore, in the event of a manufacturing capacity shortage, these competitors may be able to manufacture products when we are unable to do so.

Our Bandwidth Engine ICs compete with embedded memory solutions, stand-alone memory ICs, including both DRAM and SRAM ICs, and ASICs designed by customers in-house to meet their system requirements. Our prospective customers may be unwilling to adopt and design-in our ICs due to the uncertainties and risks surrounding designing a new IC into their systems and relying on a supplier that has limited history of manufacturing such ICs. In addition, Bandwidth Engine ICs require the customer and its other IC suppliers to implement our chip-to-chip communication protocol, the GCI interface. These parties may be unwilling to do this if they believe it could adversely impact their own future product developments or competitive advantages, or, if they believe it might complicate their development process or increase the cost of their products. In order to remain competitive, we believe we must provide unparalleled memory IC solutions with the highest bandwidth capability for our target markets, which solutions are engineered and built for high-reliability carrier and enterprise applications.

Our LineSpeed ICs compete with solutions offered by Broadcom Ltd., Inphi Corporation, M/A-COM Technology Solutions Holdings, Inc. and Semtech Corp., as well as other smaller analog signal processing companies. We also may compete with ASICs designed by customers in-house to meet their system requirements, as well as by optical module OEMs. The market for our LineSpeed products is highly competitive, and customers have a number of

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suppliers they can choose from. We must provide differentiated features with a reasonable IC power budget, while offering competitive pricing.

We depend on third-party vendors to manufacture, package, assemble and test our IC products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility for boards and system assembly. By outsourcing manufacturing, we are able to avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

We perform an ongoing review of product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meets design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers. We have achieved ISO 9001:2008 certification, and all of our manufacturing vendors have also achieved ISO 9001 certification.

As of December 31, 2016, we had 63 employees, consisting of 36 in research and development, 7 in sales and marketing, 11 in manufacturing operations and 9 in finance and administration. By location, we had 61 employees in the United States and 2 sales and marketing employees in Asia.

We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934, as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read and obtain copies of any materials we file with the SEC at the SEC’s Public Reference Room at 450 Fifth Street, NW, Washington, DC 20549. You can obtain additional information about the operation of the Public Reference Room by calling the SEC at 1.800.SEC.0330. In addition, the SEC maintains a website (www.sec.gov) that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Overview

MoSys, Inc., together with its subsidiaries ("MoSys," the "Company," "we," "our" or "us"), is a fabless semiconductor company focused on the development and sale of integrated circuits, or ICs, for the high-speed networking, communications, storage and computing markets. Our solutions deliver time-to-market, performance, signal integrity, power, area and economic benefits for system original equipment manufacturers, or OEMs. We have developed two IC product lines under the Bandwidth Engine and LineSpeed product names. Bandwidth Engine ICs integrate our proprietary 1T-SRAM high-density embedded memory with our integrated macro function technology and a highly efficient serial interface protocol resulting in a monolithic memory IC solution optimized for transaction performance. As the bandwidth requirements and amount of processing per packet increase in high-speed networking systems, critical memory access bottlenecks occur. Our Bandwidth Engine IC, with its combination of serial I/O, high-speed memory, offload functions and efficient, intelligent access, drastically increases memory accesses per second, removing these bottlenecks. In addition, the serial interface and high memory capacity reduce the board footprint, number of pins and complexity using less power. The LineSpeed IC product line, which we announced in March 2013, is comprised of non-memory, high-speed serialization-deserialization, or SerDes, I/O physical layer, or PHY, devices that ensure signal integrity between interfaces commonly referred to as clock data recovery, or CDR, or retimer functionality, which perform multiplexing to transition from one speed to another, commonly referred to as Gearbox functionality. These PHY devices reside within optical modules and networking equipment line cards designed for next-generation Ethernet and optical transport network applications.

We are currently supporting existing design win customers, primarily for Bandwidth Engine, and actively pursuing additional design wins for the use of our ICs in networking communications and data center equipment. We have established initial pricing of our IC products ordered to date, but longer-term volume prices will be subject to negotiations with our customers and may vary substantially from these initial prices.

Historically, our primary business was the design, development, marketing, sale and support of differentiated intellectual property, or IP, including embedded memory and high-speed parallel and serial I/O used in advanced systems-on-chips, or SoCs. Currently, we are focused on developing differentiated IP-rich IC products and are dedicating all our research and development, marketing and sales budget to these IC products. Royalty and other revenue generated from our existing IP

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agreements represented 58% of our total revenue in 2014 and 45% in 2015. We expect royalty and other revenue to continue to decline in 2016 both in absolute dollars and as a percentage of revenues.

Our future success and ability to achieve and maintain profitability are dependent on the marketing and sales of our IC products into networking, communications and other markets. Since the beginning of 2010, we have invested substantially all of our of our research and development resources toward development of our ICs, and, as of the end of 2012, had ceased our efforts to actively market our IP and establish license agreements for customers' new SoC development projects.

Industry Background

The amount of data being transferred by networking, storage and computing systems is increasing rapidly, primarily driven by the growth of the Internet and demand for real-time processing of bandwidth intensive applications, such as video-on-demand, Internet protocol TV, peer-to-peer and cloud computing, web2.0 applications, 4G/LTE wireless, voice-over-Internet protocol, and many others. In order to meet these demands, the network backbone, access, storage and data center infrastructure must scale in bandwidth and processing capability. In addition, system designers face the challenge of increasing the throughput of all subsystems for a variety of applications, such as video games, medical record and imaging transfers, and file sharing. These increased demands strain communication between onboard IC devices, limiting the data throughput in network switches and routers and the network backbone.

To meet these demands, carrier and enterprise networks are undergoing significant changes and, most significantly, are migrating to packet-based Ethernet networks that enable higher throughput, lower cost and uniform technology across access, core and metro network infrastructure. These networks are now being designed to deliver voice, video and high-speed Internet access on one converged, efficient and flexible network. These trends require networking systems, especially the high-speed switches and routers that primarily comprise these networks, to comply with evolving market requirements and be capable of providing new services and better quality of service while supporting new protocols and standards. To support these trends, OEM network and telecommunications equipment manufacturers, such as Alcatel-Lucent (a subsidiary of Nokia Corporation), Brocade Communications Systems, Inc., Cisco Systems, Inc., Tel. LM Ericsson, Fujitsu Ltd., Hitachi Ltd., Huawei Technologies, Juniper Networks, Inc., Nokia Corporation, and ZTE Corporation, must offer higher levels of packet forwarding rates, bandwidth density and be optimized to enable higher-density, lower power data path connectivity in the next generations of their networking systems.

Networking and telecommunications systems throughout the network must operate at higher speed and performance levels and so require new generations of packet processors and improved memory subsystems, as well as new physical interface products, to enable system performance. These systems and their component line cards generally need to support aggregate rates of 100 gigabits per second, or Gbps, and above to meet the continued growth in network traffic. Cloud services have accelerated this transition with applications such as security. Data centers and access equipment that were previously aggregating slower traffic such at 1Gbps to 10Gbps, and 40Gbps, now are being designed to aggregate traffic at 10Gbps to 100Gbps, or more. The transition to 100 Gbps networks has begun, and 100 Gbps networks are expected to grow rapidly over the coming years.

Several types of semiconductors are included on each line card, including PHY, one or more packet processors and multiple memory chips. Packet processors are complex ICs or IC chipsets that perform high speed processing for functions, such as traffic routing, shaping, metering, billing, statistics, detection and steering. The line cards use various types of memory ICs to facilitate temporary packet storage and assist in the analysis and tracking of information embedded within each packet flowing through the processors. After a packet enters the line card through a PHY, a packet or data processor helps separate the packet into smaller pieces for rapid analysis. Typically, the data is broken up into the packet header, which contains vital information on packet destination and type, such as the Internet

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protocol address, and the payload, which contains the data being sent. Generally, the line card operations must occur at full data rates and typically require accessing memory ICs many times. Simultaneously, the packet's payload, which may be substantially larger than the packet header, is also stored in memory ICs until processing is complete and the packet can re-combine and be sent to its next system destination. Within the line card, communication between the packet processor and memory ICs occurs through an interface consisting of combinations of physical pins on each type of chip. These pins are grouped together in a parallel or a serial architecture to form a pathway, called a bus, through which information is transferred from one IC to the next.

Today, the majority of physical buses that connect networking equipment and components use a parallel architecture to communicate between processors and memory ICs, which means information can travel only in one direction and in one instance at a time. As processing speeds increase, the number of pins required and the speed of the bus in a parallel architecture become a limitation on system performance and capability. In contrast, the number of connections is reduced substantially across fewer, higher-rate pins in a serial architecture, and data is transferred simultaneously in both directions. Data transfer rates with high-speed serial bus architectures and more advanced I/O protocols are limited by the capabilities of the various ICs included on the line card, thus leading to bottlenecks when these ICs perform inadequately. In order to remove these bottlenecks and meet next-generation bandwidth requirements, the line card ICs must support high-speed serial bus architectures and these more advanced I/O protocols.

Most networking and communication systems sold and in operation today include line cards that process data at speeds ranging from 10 Gbps, to 100 Gbps, and support many aggregated slower ports. To accommodate the substantial and growing increase in demand for networking communications and applications, networking systems manufacturers are developing and bringing to market next-generation systems that run at aggregate speeds of 100 to 400 Gbps or more with developments underway to scale to thousands of Gbps, or terabits, per second. However, although processor performance in applications such as computing and networking has continued to double nearly every 18 months, or even sooner, the performance of memory technology has generally been able to double only once every 10 years. Existing memory IC solutions based on parallel I/O architecture easily support speeds up to 40 Gbps, but are not optimal for meeting speeds of 100 Gbps and beyond due to system-level limitations for pin counts, power and performance. These networking and communications systems are generally comprised of a chassis populated by four to 16 line cards. Often, these systems are shipped to customers with only a portion of the line card slots populated, and the customer will add additional line cards subsequently to increase system performance and capacity.

Each line card requires a significant amount of memory to support its processing capabilities. Traditional external memory IC solutions currently used on line cards include both dynamic random access memory, or DRAM, and static random access memory, or SRAM. Line cards in networking systems use both specialized, high-performance DRAM ICs, such as reduced-latency DRAM, or RLDRAM, low-latency DRAM, or LLDRAM, and commodity DRAM, such as double data rate, or DDR ICs. In addition, networking systems use higher-performance SRAM ICs such as quad data rate, or QDR SRAM. Substantially all of these traditional memory IC solutions use parallel interfaces, which are slower than serial interfaces, so we believe they will be increasingly challenged to meet the performance, pin count, area and power requirements as networking systems expand beyond 100 Gbps. The result is a gap between processor and memory performance. To meet the higher performance requirements being demanded by the industry, while using current components and architectural approaches, system designers must add more discrete memory ICs to the line cards and/or add more embedded memory on the packet processor. This results in higher cost and power consumption, the use of more space on the line cards and additional communication interference between the ICs, which in turn results in additional bandwidth limitation problems. We believe our Bandwidth Engine family of products is well suited to address these challenges and replace these traditional memory solutions.

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In addition, each line card requires PHY products to provide interoperability and signal integrity functions. As network speeds increase beyond 100Gbps, the serial data rates are transitioning from 10Gbps to 25Gbps. This means that the signal integrity challenges (maintaining the quality of the electrical signals) of moving these high speed signals around within line cards, or between line cards and systems using fiber optic or copper cable, increase as data rates increase. These networking systems often use copper or optical modules to modify signals for transmission over longer distances ranging from tens of meters to thousands of kilometers. Optical modules convert electrical signals to optical signals for transportation over longer distances from one system to another system. Because of the challenges arising from the increase in network speeds, new 100Gbps standards have emerged that specify a CDR or retimed interface on optical modules, which was not the case at 10Gbps based interfaces. Each 100Gbps module and above using 25Gbps per lane will require a CDR/retimer function inside the module to meet these requirements. In addition, the systems themselves also require additional support to move signals between the module and the system, and these challenges become more acute as the distance increases. Our LineSpeed products address these new line card and optical module challenges by providing unique signal integrity and feature sets that align with the industry standards, as well as provide backward compatibility for the previous data rates. We believe our LineSpeed PHY products are well suited ensure the quality of signals and/or increase the transmission distance for both short reach (e.g., between ICs on a line card) or long-reach (e.g., between line cards or systems).

We have developed our Bandwidth Engine and LineSpeed families of ICs to synergistically address the need for high-speed data access and throughput currently confronting networking system designers. We expect our IC products to meet the increasing demands placed on conventional memory technology used on the line cards in high-bandwidth networking systems. We believe that our products and technology are well positioned as replacements for existing IC solutions in order to meet the needs of the next-generation networking systems that will require a large number of packet lookups and to support aggregated rates greater than 100 Gbps.

Our Approach

Our historical business was focused on the licensing of our proprietary 1T-SRAM and SerDes I/O technologies. We have leveraged our proprietary IP to design our Bandwidth Engine and LineSpeed IC product families to help networking OEMs address the growing bottlenecks in system performance. We have incorporated critical features into our product families to accomplish this objective.

On-chip Functionality

One significant performance bottleneck in any network line card is the need to transfer data between discrete ICs. Many of these data-transfer operations are iterative in nature, requiring subsequent, back-to-back accesses of the memory IC by the processor IC. Our Bandwidth Engine ICs include an arithmetic logic unit, or ALU, which enables the Bandwidth Engine IC to perform mathematical operations on data. Moving certain processing functions from the processor IC to the Bandwidth Engine IC through the use of this embedded ALU, reduces the number of I/O transactions and frees the processor IC to perform other important networking or micro-processing functions.

High-Performance Interface

High-speed, efficient interface I/Os are critical building blocks to meet high data transfer rate requirements for communication between ICs on network line cards. We believe that current networking system requirements necessitate an industry transition from parallel to serial I/O. As a result, semiconductor companies are increasingly turning to serial I/O architectures to achieve needed system performance. For example, high-performance ICs that are sold into wide markets, such as field programmable gate arrays, or FPGAs, and network processing units, NPUs, are using serial I/Os to ensure they can compete with custom designed application specific ICs, or ASICs, by matching their

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performance. Using serial I/O, IC developers also are able to reduce pin count (the wired electrical pins that connect an IC to the network line card on which it is mounted) on the IC. With reducing geometries, the size of most high-performance ICs is dictated by the number of pins required, rather than the amount of logic and memory embedded in the chip. As a result, using serial I/O facilitates cost reduction and reduced system power consumption, while improving the performance of both the IC itself and the overall system. While SerDes I/Os provide significantly enhanced performance over parallel I/Os, SerDes I/Os traditionally have had higher power consumption, which is a challenge for IC designers. Our SerDes I/Os, however, are tuned for low power consumption to meet our customers' stringent power consumption requirements.

We make our I/O technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering their development and validation costs. Interoperability reduces development time, thereby reducing the overall time to market of our customers' systems.

Analog Design Capabilities

We have invested in personnel needed to define, design and market high-performance analog IC products. We have built a team of experienced engineers who combine industry expertise with advanced semiconductor design expertise to meet customer requirements and develop new products to bring to market. We intend to leverage these capabilities to achieve new levels of integration, power reduction and performance, enabling our customers to achieve differentiation in their end systems. We initially developed our team of analog engineers to develop the SerDes I/O used in our Bandwidth Engine families of products. We leveraged the capabilities of this team to produce our LineSpeed IC products, which are primarily comprised of analog circuitry.

GigaChip Interface Protocol

In addition to the physical characteristics of the serial I/O, the protocol used to transmit data is also an important element that impacts speed and performance. To address this and complement our Bandwidth Engine devices, we have developed the GigaChip Interface®, or GCI, which is an open-interface transport protocol optimized for efficient chip-to-chip communications. The GCI electrical interface is compatible with the current industry standard (Common Electrical Interface, release #11, or CEI-11G-SR and XFI) to simplify electrical interoperability between devices. GCI can enable highly efficient serial chip-to-chip communications, and its transport efficiency averages 90% for the data transfers it handles. GCI is included in our Bandwidth Engine ICs, and is offered to customers and prospective partners on terms intended to encourage widespread adoption.

High-Performance and High-Density Memory Architecture

The high-density of our proprietary 1T-SRAM technologies stems from the use of a single-transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM, or 6T-SRAM. Embedded memory utilizing our 1T-SRAM technologies typically provides speeds essentially equal to or greater than the speeds of traditional SRAM and DRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than embedded 6T-SRAM technology. Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generate less heat than traditional SRAM when operating at the same speed. This reduces system level heat dissipation and enables reliable operation using lower cost packaging.

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Our Strategy

Our primary business objective is to be an IP-rich fabless semiconductor company offering ICs that deliver unparalleled memory bandwidth performance for packet processing and improved signal integrity performance for networking, security and data center systems. The key components of the expansion of our strategic plan to become an IC supplier include the following strategies:

Target Large and Growing Markets

Our initial strategy is to target the multi-billion dollar networking telecommunications, security and data center OEM equipment markets, and we have developed products to support the growth in 100 Gbps and higher networking speeds. We are currently supporting approximately 25 existing customers, with whom we have achieved over 85 design wins, which reflects broadening acceptance of our products. We define a design win as the point at which a customer has made a commitment to build a board against the fixed schematic for his system, and this board will utilize our IC products. We continue to actively pursue additional design wins for the use of our ICs in our target markets. We believe our design wins represent the potential for significant future revenues. With limited history to date, however, we cannot estimate how much revenue each design win is likely to generate, or how much revenue all of these (and future design wins) are likely to generate. For example, our first design wins from 2012 and 2013 are starting to ramp into production, and, while we cannot predict how steep these ramps might be, we expect our revenues from them to grow in successive periods over the next few years. There is no assurance that these customer designs will be shipped in large volume by our customers to their customers, however.

Leverage Technologies to Create New Products

Our strategy is to combine our proprietary IP and design and applications expertise to address the needs of several upcoming generations of advanced networking systems. We believe an IC combining our 1T-SRAM and serial I/O with logic, such as in an ALU, and other functions can provide a system-level solution and significantly improve overall system performance at lower cost while using less power. We also seek to leverage our high-speed serial I/O to create non-memory denominated ICs, such as our LineSpeed products. Our initial LineSpeed products targeted the line card and the same customers as our Bandwidth Engine products. This has given us the opportunity to provide both memory and PHY solutions during the sale process. In 2013, we introduced our first LineSpeed products to address the requirements new industry standards were placing on optical modules, as well as line cards.

Expand Adoption of the GigaChip Interface Protocol

We have provided our GCI interface protocol as an open industry standard that may be designed into other ICs in the system, as we believe this will further enable serial communication on network line cards and encourage adoption of our Bandwidth Engine IC products. A number of IC providers and partners have publicly announced their support of GCI and Bandwidth Engine, including the largest FPGA providers, Altera Corporation (a subsidiary of Intel Corporation), Xilinx, Inc., and EZchip Semiconductor Ltd. (a subsidiary of Mellanox Technologies Ltd.), with whom we work closely to support common customers. In addition, multiple networking systems companies, including actual and prospective customers, have adopted GCI.

Build Long-Term Relationships with Suppliers of Packet Processors

We believe that having long-term relationships with packet processor providers is critical to our success, as such relationships may enable us to reduce our time-to-market, provide us with a competitive advantage and expand our target markets. A key consideration of network system designers is to demonstrate interoperability between our Bandwidth Engine IC and the packet processors utilized in their systems. To obtain design wins for our Bandwidth Engine IC, we must demonstrate this interoperability, and also show that our IC works optimally with the packet processor to achieve the

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performance requirements. In addition, our current strategy requires packet processor suppliers to adopt our GCI interface. To that end, we have been working closely with FPGA, ASIC and NPU providers, to enable interoperability between our Bandwidth Engine IC products and their high-performance products. To facilitate the acceptance of our Bandwidth Engine ICs, we have made available development and characterization kits for system designers to evaluate and develop code for next-generation networking systems. Our characterization kits are fully-functional hardware platforms that allow FPGA and ASIC providers, and their customers, to demonstrate interoperability of the Bandwidth Engine IC with the ASIC or FPGA the designers use within their networking systems. Our recent announcement of the third-generation Bandwidth Engine Z30 device, designed for interoperability with the EZ-chip NPS-400, is an example and direct result of this strategy.

Our Products

Bandwidth Engine

The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element. Our Bandwidth Engine ICs combine: (1) our proprietary high-density, high-speed, low latency embedded memory, (2) our high-speed serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM memory and serial I/O with logic and other intelligence functions provides a system-level solution and significantly improves overall system performance at lower cost, size and power consumption. Our Bandwidth Engine ICs can provide up to and over 4.5 billion memory accesses per second, which is more than twice the performance of current memory-based solutions. They also can enable system designers to significantly narrow the gap between processor and memory IC performance. Customers that design Bandwidth Engine ICs onto the line cards in their networking systems will re-architect their systems at the line-card level and use our product to replace traditional memory solutions. When compared with existing commercially available solutions, our Bandwidth Engine ICs may:

• provide up to four times the performance;

• reduce power by approximately 50%;

• reduce cost by greater than 50%; and

• result in a dramatic reduction in IC pin counts on the line card.

Our first generation Bandwidth Engine IC products contain 576 megabytes, or MB, of memory and use a serial I/O with up to 16 lanes operating at up to 10.3 Gbps per lane. Variations of this IC can have up to two interface ports, with up to eight serial receiver and eight serial transmitter lanes per port for a total of 16 lanes of 10.3 Gbps SerDes interface. These ICs include an ALU, which can perform read-modify-write operations. We have been shipping our initial Bandwidth Engine products since 2012.

Our second generation Bandwidth Engine IC products contain 576 MB of memory and use serial I/O with up to 16 lanes operating at up to 15 Gbps per lane. In addition to a speed improvement of up to 50%, the architecture will enable several family member parts with added specialized features. To date, we have announced three unique devices in this product family:

• MSR620 with burst features optimized for oversubscription buffer applications;

• MSR720 with a write cache and memory coherency capability that allows for deterministic look-ups optimized for state and queue type applications; and

• MSR820 with increased intelligence for lookup, metering and statistics applications by adding dual counters, atomic and extensive metering functions.

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We have been shipping our Bandwidth Engine 2 IC products since 2013.

Our third generation Bandwidth Engine IC products contain 1152 MB of memory and use serial I/O with up to 16 lanes operating at up to 30 Gbps per lane. Bandwidth Engine 3 targets support for packet-processing applications with up to five billion memory single word accesses per second, as well as burst mode to enable full duplex buffering up to 400Gbps for ingress, egress and oversubscription applications. To date, we have announced three unique devices in this product family:

• MSR630 enables high rate lookup or high-performance buffer capabilities; and

• MSR830 offers additional offload capabilities for functions such as statistics and metering to increase performance and add features for next-generation networking and communications equipment; and

• MSRZ30 builds upon the capabilities and performance of the MSR830, with data rates, interface protocol and data structures that are optimized for the EZchip NPS-400 network processing unit, or NPU, and can increase memory bandwidth by up to 50%.

We commenced sampling of these products in the first quarter of 2016.

The devices provide benefits of size, power, pin count and cost savings to our customers.

LineSpeed

Our first generation LineSpeed products consist of single-chip PHY ICs, including a 100G multi-mode gearbox and a 100G quad retimer. These devices are designed to support 10, 40 and 100Gbps standards for high-density line cards or modules for next generation ethernet and optical transport network applications. These devices are capable of supporting both short and long reach connections across different specifications. We have developed these PHY ICs to provide the CDR function and to provide signal conversion from lower rates to higher rates both on the line card and within the optical module. We have defined performance and form factor (sizes) for specific devices for optimization of features and performance to solve challenges on the line card and in the optical module. We introduced and began sampling these devises in 2013.

Our second generation of LineSpeed products consists of our 100G low power retimer, which is optimized for ultra low power consumption, integrated test features and small size. The low-power retimer is primarily targeting opportunities in 100G CFP2, CFP4 and QSFP28 optical modules and active copper cables. We introduced and began sampling this product in 2014.

We announced our third generation of our LineSpeed products, the Flex family of 100G PHYs, and sampled first devices in the second half of 2015. These PHY devices are designed to support the latest industry standards and include gearbox, Multi-Link Gearbox, or MLG, and high density CDR/retimer devices designed to enable existing and next generation Ethernet and OTN line card applications to support the latest high-density electrical and optical interfaces. To date, we have announced four unique devices in this product family:

• MSH320, a 100Gbps Gearbox with RS-FEC: For adapting 10x10 to 4x25 from 100Gbps optical standards to a host ASIC, MAC/Framer, NPU or FPGA with 10x10G interfaces. The MSH320 includes an integrated Reed-Solomon forward error correction, or RS-FEC, option to enable systems to also support new electrical and optical standards. The device also includes a 10x10Gbps retimer to allow seamless support of 10 and 40Gbps interfaces;

• MSH225, a 10 Lane Full-Duplex Retimer: For high-density retiming applications where the line rates may be up to 28Gbps per lane and connect to host ASIC, framer, NPU or FPGA ICs equipped with 25Gbps interfaces. Each one of the 20 total independent lanes can be configured to support 10, 25, 40 or 100Gbps standards. The MSH225 integrates optional 100Gbps RS-FEC capability and includes a unique redundant link mode feature to support redundancy, scaling or monitoring features;

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• MSH322, a 100Gbps Multi-Link Gearbox for Line Cards for support of high-density, independent 10GE and 40GE interfaces multiplexed into a 100GE (4x25Gbps) host interface, while supporting the latest optical industry standards. The device enables line cards with high-density switches based on 25Gbps interfaces to support two times the density of 10 and 40Gbps ports; and

• MSH321, a derivative Multi-Link Gearbox built into a highly compact package and optimized layout to support the MLG function in module and compact daughter card applications.

We do not anticipate significant revenues from our LineSpeed ICs until 2017 or later. While we have a robust pipeline of design win opportunities, to date, less than 10% of our design wins claimed are for our LineSpeed products, and we expect these customers to take a minimum of 18 months to commence production.

IP Licensing and Distribution

Historically, we have offered our memory and I/O technologies on a worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies through product development, technology licensing and joint marketing relationships. We licensed our IP technology to semiconductor companies who incorporated our technology into ICs that they sold to their customers. As a result of the change in our corporate strategy, since early 2012, our IP licensing activities have been limited, and we expect this to continue. However, during 2015, 45% of our total revenues were generated from royalties related to our existing licensing arrangements, as we continue to collect royalties from 1T- SRAM licensees. Licensing and royalty revenues have been declining since 2010, and we expect continued decline in 2016.

Research and Development

Our ability to compete in the future depends on successfully improving our technology to meet the market's increasing demand for higher performance and lower cost requirements. We have assembled a team of highly skilled engineers whose activities are focused on developing higher density, higher bandwidth, higher speed and lower cost next generation IC products. Development of our IC products requires specialized chip design and product engineers, as well as significant fabrication and testing costs, including mask costs, as we bring these products to market. We expect our significant future research and development activities to include:

• designing next generation ICs with larger memory blocks and higher-speed SerDes;

• developing versions of our Bandwidth Engine ICs with alternative features, such as lower-speed SerDes, increased chip-level intelligence or smaller memory blocks to allow us to serve a broader range of applications and systems;

• developing derivative versions of our LineSpeed ICs to meet customer demands; and

• developing new products that can leverage our proprietary IP portfolio and expand our market opportunity.

No development efforts are being dedicated to creating new or enhanced technology solely for use in licensing offerings.

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Sales and Marketing

We believe that networking and communications systems OEMs typically prefer to extend the use of traditional memory solutions and their parallel interfaces, despite performance and costs challenges and are reluctant to change their technology platforms and adopt new designs and technologies, such as serial interfaces, which are an integral part of our product solutions. Therefore, our principal selling and marketing activities to date have been focused on persuading these OEMs and key component suppliers that our solutions provide critical performance advantages, as well as on securing design wins with them.

Our sales and marketing personnel are located in the United States, Japan and China. In addition to our direct sales team, we sell through sales representatives and distributors in the United States and Asia. We also have eight applications engineers who support our customer engagements and work closely with our engineering team on product definition. For our products, our applications engineers must engage with the customers' system architects and designers to propose our IC and IP solutions such as the GCI Interface, to address their systems challenges.

In the markets we serve, the time from initial customer engagement to design win to production volume shipments can range from 18-36 months. Networking and communications systems can have a product life from a few years to over 10 years once a product like ours has been designed into the system.

Our revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue. For the year ended December 31, 2015, Alcatel-Lucent, Taiwan Semiconductor Manufacturing Co., Ltd., or TSMC and Kogent, Inc., our Japanese IC distributor, represented 34%, 31% and 12% of total revenue, respectively. For the year ended December 31, 2014, TSMC, Kogent, Inc. and Broadcom Ltd., represented 34%, 31% and 11% of total revenue, respectively. For the year ended December 31, 2013, TSMC and Broadcom Ltd., licensees of our memory IP, represented 41% and 13% of total revenue, respectively.

Customers in North America accounted for 51%, 28% and 30% of our revenues for the years ended December 31, 2015, 2014 and 2013, respectively. Customers in Japan accounted for 15%, 36% and 27% of our revenues for the years ended December 31, 2015, 2014 and 2013, respectively. Customers in Taiwan accounted for 32%, 35% and 42% of our revenues for the years ended December 31, 2015, 2014 and 2013, respectively. Our remaining revenues were primarily from customers in the rest of Asia and in Europe.

Intellectual Property

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success, and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of December 31, 2015, we held approximately 67 U.S. and 30 foreign patents on various aspects of our technology, with expiration dates ranging from 2016 to 2035. We currently have approximately 29 pending patent applications in the U.S. and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

In December 2011, we sold 43 United States and 30 related foreign memory technology patents for $35 million in cash pursuant to a patent purchase agreement. Under the agreement, we retained a license to all of the sold patents that is unlimited with respect to our development, manufacturing and distribution of our Bandwidth Engine IC product line and any other proprietary products that we develop as long as they are not DRAM ICs. We also retained the rights necessary to renew existing

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1T-SRAM licenses and to grant licenses similar in scope to identified foundries. We also retained rights to grant licenses for our second source purposes, to enable certain kinds of technology development and, to a limited extent, for certain ASIC products that incorporate one of our technology macros. However, the patent purchase agreement limits our rights to grant licenses under the sold patents outside the scope of our retained license and, in particular, limits the number of future licenses of 1T-SRAM memory technology that we can grant to developers of SoCs, which used to be the principal focus of our 1T-SRAM licensing activities.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, "Risk Factors."

Competition

The markets for our products are highly competitive. We believe that the principal competitive factors are:

• processing speed and performance;

• density and cost;

• power consumption;

• reliability;

• interface requirements;

• ease with which technology can be customized for and incorporated into customers' products; and

• level of technical support provided.

We believe that we can compete favorably with respect to each of these criteria. Our proprietary 1T-SRAM embedded memory and high-speed serial I/O IP can provide our Bandwidth Engine ICs with a competitive advantage over alternative devices. Alternative solutions are either DRAM or SRAM-based and can support either the memory size or speed requirements of high-performance networking systems, but generally not both. DRAM solutions provide a significant amount of memory at competitive cost, but DRAM solutions do not have the required fast access and cycle times to enable high-performance. The DRAM solutions currently used in networking systems include RLDRAM from Micron Technology, Inc., or Micron, and Integrated Silicon Solutions, Inc., LLDRAM from Renesas and DDR from Samsung Electronics Co., Ltd., Micron and others. In addition, Micron has a hybrid memory cube DRAM product, which consists of multiple DRAMs connected with a serial interface. SRAM solutions can meet high-speed performance requirements, but often lack adequate memory size. The SRAM solutions currently used in networking systems primarily include QDR or similar SRAM products from Cypress Semiconductor Corporation and GSI Technology, Inc. The majority of the currently available SRAM and DRAM solutions use a parallel, rather than a serial I/O. To offset these drawbacks, system designers generally must use more discrete memory ICs, resulting in higher power consumption and greater utilization of space on the line card.

Our competitors include established semiconductor companies with significantly longer operating histories, greater name recognition and reputation, large customer bases, dedicated manufacturing facilities and greater financial, technical, sales and marketing resources. This may allow them to respond more quickly than us to new or emerging technologies or changes in customer requirements.

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Many of our competitors also have significant influence in the semiconductor industry. They may be able to introduce new technologies or devote greater resources to the development, marketing and sales of their products than we can. Furthermore, in the event of a manufacturing capacity shortage, these competitors may be able to manufacture products when we are unable to do so.

Our Bandwidth Engine ICs compete with embedded memory solutions, stand-alone memory ICs, including both DRAM and SRAM ICs, and ASICs designed by customers in-house to meet their system requirements. Our prospective customers may be unwilling to adopt and design-in our ICs due to the uncertainties and risks surrounding designing a new IC into their systems and relying on a supplier that has limited history of manufacturing such ICs. In addition, Bandwidth Engine ICs require the customer and its other IC suppliers to implement our chip-to-chip communication protocol, the GCI interface. These parties may be unwilling to do this if they believe it could adversely impact their own future product developments or competitive advantages, or, if they believe it might complicate their development process or increase the cost of their products. In order to remain competitive, we believe we must provide unparalleled memory IC solutions with the highest bandwidth capability for our target markets, which solutions are engineered and built for high-reliability carrier and enterprise applications.

Our LineSpeed ICs compete with solutions offered by Broadcom Ltd., Inphi Corporation, M/A-COM Technology Solutions Holdings, Inc. and Semtech Corp., as well as other smaller analog signal processing companies. We also may compete with ASICs designed by customers in-house to meet their system requirements, as well as by optical module OEMs. The market for our LineSpeed products is highly competitive, and customers have a number of suppliers they can choose from. We must provide differentiated features with a reasonable IC power budget, while offering competitive pricing.

Manufacturing

We depend on third-party vendors to manufacture, package, assemble and test our IC products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility for boards and system assembly. By outsourcing manufacturing, we are able to avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

We perform an ongoing review of product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meets design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers. We have achieved ISO 9001:2008 certification, and all of our manufacturing vendors have also achieved ISO 9001 certification.

Employees

As of December 31, 2015, we had 104 employees, consisting of 75 in research and development, 8 in sales and marketing, 11 in manufacturing operations and 10 in finance and administration. By location, we had 81 employees in the United States, 21 in our development center in India and 2 sales and marketing employees in Asia. In January 2016, we committed to effect a reduction in our workforce and associated operating expenses, net loss and cash burn and to realign resources, as we have substantially concluded development of new products, including our third generation Bandwidth Engine IC product family, and expect to bring these products to market in 2016. We have reduced United States headcount by approximately 13 people and will cease operations at our subsidiary in Hyderabad, India in the first half of 2016.

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Available Information

We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934 as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read and obtain copies of any materials we file with the SEC, at the SEC's Public Reference Room at 450 Fifth Street, NW, Washington, DC 20549. You can obtain additional information about the operation of the Public Reference Room by calling the SEC at 1.800.SEC.0330. In addition, the SEC maintains a website (www.sec.gov) that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Executive Officers

The names of our executive officers and certain information about them are set forth below:

Leonard Perham 72 President and Chief Executive Officer James W. Sullivan 47 Vice President of Finance and Chief Financial Officer Thomas Riordan 59 Chief Operating Officer and Executive Vice President John Monson 53 Vice President of Marketing and Sales

Leonard Perham. Mr. Perham was appointed President and Chief Executive Officer in November 2007. Mr. Perham was one of the original investors in MoSys and served on our Board of Directors from 1991 to 1997. In 2000, Mr. Perham retired from Integrated Device Technology, Inc., or IDT, where he served as Chief Executive Officer from 1991 and President and board member from 1986. From March 2000 to February 2012, Mr. Perham served as a member of or chairman of the board of directors of NetLogic Microsystems, a fabless semiconductor company. Prior to joining IDT, Mr. Perham was President and CEO of Optical Information Systems, Inc., a division of Exxon Enterprises. He was also a member of the founding team at Zilog, Inc. and held management positions at Advanced Micro Devices and Western Digital. Mr. Perham received a Bachelor of Science degree in Electrical Engineering from Northeastern University.

James W. Sullivan. Mr. Sullivan became our Vice President of Finance and Chief Financial Officer in January 2008. From July 2006 until January 2008, Mr. Sullivan served as Vice President of Finance and Chief Financial Officer at Apptera, Inc., a venture-backed company providing software for mobile advertising, search and commerce. From July 2002 until June 2006, Mr. Sullivan was the Chief Financial Officer at 8x8, Inc., a provider of voice over internet protocol communication services. Mr. Sullivan's prior experience includes various positions at 8x8, Inc. and PricewaterhouseCoopers LLP. He received a Bachelor of Science degree in Accounting from New York University and is a Certified Public Accountant.

Thomas Riordan. Mr. Riordan became our Chief Operating Officer and Executive Vice President in May 2011. Prior to joining the Company, Mr. Riordan was President and Chief Executive Officer of Exclara, a fabless semiconductor supplier of ICs for solid-state lighting from 2006 until 2010. From 2000 to 2004, Mr. Riordan served as Vice President of PMC-Sierra's microprocessor division. Mr. Riordan joined PMC-Sierra in August 2000 when it purchased Quantum Effects Devices, which he had co founded and served as President and Chief Executive Officer. Mr. Riordan serves on the board of directors of Mellanox Technologies. Mr. Riordan holds Bachelor of Science and Master of Science degrees in Electrical Engineering as well as a Bachelor of Arts degree in Government from the

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University of Central Florida and has done post-graduate work in Electrical Engineering at Stanford University.

John Monson. Mr. Monson became our Vice President of Marketing in February 2012. In early 2014, he assumed, on a permanent basis, additional responsibilities for our sales and business development activities and became our Vice President of Marketing and Sales. Prior to joining the Company, Mr. Monson was Vice President of Marketing for Mellanox Technologies, a supplier of interconnect solutions and services, from 2009 to 2012. From 2007 to 2008, Mr. Monson was Vice President of the EDC/PhyOptik business line at Inphi Corporation. He joined Inphi Corporation through a business unit acquisition of Scintera Networks, where he was Vice President of Sales and Marketing from 2005 to 2007. Previously, he held various management positions at PMC-Sierra, Inc., Lucent Technologies and AT&T Microelectronics. Mr. Monson received a Bachelor of Science degree in Electrical Engineering from the University of Minnesota.

Overview

MoSys, Inc., together with its subsidiaries (MoSys, the Company, we, our or us), is a fabless semiconductor company focused on the development and sale of integrated circuits, or ICs, for the high-speed networking, communications, storage and computing markets. Our solutions deliver time-to-market, performance, power, area and economic benefits for system original equipment manufacturers, or OEMs. We have developed two IC product lines under the Bandwidth Engine and LineSpeed product names. Bandwidth Engine ICs combine our proprietary 1T-SRAM high-density embedded memory, integrated macro functions and high-speed serial interface, or I/O, with our intelligent access technology and a highly efficient interface protocol. As the bandwidth requirements and amount of packet processing increase in high-speed networking systems, critical memory access bottlenecks can occur. Our Bandwidth Engine IC, with its combination of serial I/O, high-speed memory, offload functions and efficient, intelligent access, drastically increases memory accesses per second, removing these bottlenecks. The LineSpeed IC product line, which was announced in March 2013, is comprised of non-memory, high-speed SerDes I/O devices with gearbox and retimer functionality, which convert lanes of data received on line cards or by optical modules into different configurations and/or ensure signal integrity. These ICs are designed for next-generation Ethernet and optical transport network applications. We are currently supporting existing design win customers and actively pursuing additional design wins for the use of our ICs in networking and communication equipment. We have established initial pricing of our IC products ordered to date, but longer-term volume prices will be subject to negotiations with our customers and may vary substantially from these initial prices.

Historically, our primary business was the design, development, marketing, sale and support of differentiated intellectual property, or IP, including embedded memory and high-speed parallel and serial I/O used in advanced systems-on-chips, or SoCs. Currently, we are focused on developing differentiated IP-rich IC products and are dedicating all our research and development, marketing and sales budget to these IC products. While royalty and other revenue generated from our existing IP agreements represented 58% of our total revenue in 2014, we expect royalty and other revenue to decline in 2015.

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Our future success and ability to achieve and maintain profitability will be dependent on the marketing and sales of our IC products into networking, communications and other markets. Since the beginning of 2010, we have invested substantially all of our of our research and development resources towards development of our ICs, and as of the end of 2012 had ceased our efforts to actively market our IP and establish license agreements for customers' new SoC development projects.

Industry Background

The amount of data being transferred by networking, storage and computing systems is increasing rapidly, primarily driven by the growth of the Internet and demand for real-time processing of bandwidth intensive applications, such as video-on-demand, Internet protocol TV, peer-to-peer and cloud computing, web2.0 applications, 4G/LTE wireless, voice-over-Internet protocol, and many others. In order to meet these demands, the network backbone, access, storage and data center infrastructure must scale in bandwidth and processing capability. In addition, system designers face the challenge of increasing the throughput of all subsystems for a variety of applications, such as video games, medical record and imaging transfers, and file sharing. These increased demands strain communication between onboard IC devices, limiting the data throughput in network switches and routers and the network backbone.

To meet these demands, carrier and enterprise networks are undergoing significant changes and, most significantly, are migrating to packet-based Ethernet networks that enable higher throughput, lower cost and uniform technology across access, core and metro network infrastructure. These networks are now being designed to deliver voice, video and high-speed Internet access on one converged, efficient and flexible network. These trends require networking systems, especially the high-speed switches and routers that primarily comprise these networks, to comply with evolving market requirements and be capable of providing new services better quality of service while supporting new protocols and standards. To support these trends, OEM network and telecommunications equipment manufacturers, such as Alcatel-Lucent, Brocade Communications Systems, Inc., Cisco Systems, Inc., Tel. LM Ericsson, Fujitsu Ltd., Hitachi Ltd., Huawei Technologies, Juniper Networks, Inc., Nokia Siemens Networks, and ZTE Corporation, must offer higher levels of packet forwarding rates, bandwidth density and be optimized to enable higher-density, lower power data path connectivity in the next generations of their networking systems. This in turn requires new generations of packet processors and improved memory subsystems to enable system performance in support of these increased demands.

Networking and telecommunications systems must operate at higher speed and performance levels. These systems and their component line cards will generally need to support aggregate rates of 100 Gbps and above to meet the continued growth in network traffic. Several types of semiconductors are included on each line card, including physical interface electronics, one or more packet processors and multiple memory chips. Packet processors are complex ICs or IC chipsets developed using field programmable gate arrays, or FPGAs, application- specific integrated circuits, or ASICs, application specific standard products, or ASSPs, or network processing units, or NPUs, that perform high speed processing for functions, such as traffic routing, shaping, metering, billing, statistics, detection and steering. The line cards use various types of memory ICs to facilitate the temporary storage and assist in the analysis and tracking of information embedded within each packet flowing through the processors. After a packet enters the line card through a physical interface, a packet or data processor helps separate the packet into smaller pieces for rapid analysis. Typically, the data is broken up into the packet header, which contains vital information on packet destination and type, such as the Internet protocol address and payload, which contains the data being sent. Generally, the line card operations must occur at full data rates and typically requires accessing memory ICs many times. Simultaneously, the packet's payload, which may be substantially larger than the packet header, is also stored in memory ICs until processing is complete and the packet can re-combined and sent from the system. Within the line card, communication between the packet processor and memory ICs occurs through

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either a parallel or serial interface. Combinations of physical pins on each type of chip are grouped together in a parallel or serial architecture to form a pathway, called a bus, through which information is transferred from one IC to the next.

Today, the majority of physical buses that connect networking equipment and components use a parallel architecture to communicate between processors and memory ICs, which means information can travel only in one direction and in one instance at a time. As processing speeds increase, in a parallel architecture the number of pins required and the speed of the bus become a limitation on system performance and capability. In a serial architecture, the number of connections is reduced substantially across fewer, higher-rate pins and data is transferred simultaneously in both directions. High speed serial bus architectures and more advanced I/O protocols must be supported by the various ICs included on the line card in order to remove the bottleneck and meet next generation bandwidth requirements.

The majority of networking systems sold and in operation today includes line cards that process data at speeds of 10 gigabits per second, or Gbps, to 100 Gbps, supporting many aggregated slower ports. To accommodate the substantial and growing increase in demand for networking communications and applications, networking systems manufacturers are developing and bringing to market next-generation systems that run at aggregate speeds of 100 to 400 Gbps with plans to scale to thousands of Gbps, or Terabits, per second. However, although processor performance in applications such as computing and networking has continued to nearly double every 18 months, or even sooner, the performance of memory technology has generally been able to double once every 10 years. Existing memory IC solutions based on parallel I/O architecture easily support speeds up to 40 Gbps, but are not optimal for meeting speeds of 100 Gbps and beyond due to system-level limitations for pin counts, power and performance.

Traditional memory solutions currently used on line cards include both dynamic random access memory, or DRAM, and static random access memory, or SRAM, IC solutions. Line cards in networking systems use both specialized, high-performance DRAM ICs, such as reduced-latency DRAM, or RLDRAM, low-latency DRAM, or LLDRAM, and commodity DRAM, such as double data rate, or DDR ICs. In addition, networking systems use higher-performance SRAM ICs such as quad data rate, or QDR SRAM.

Substantially all of these DRAM and SRAM memory ICs use parallel interfaces, which are slower than serial interfaces and will be increasingly challenged to meet the performance, pin count, area and power requirements as networking systems expand beyond 100 Gbps. The result is a gap between processor and memory performance. To meet the higher performance requirements being demanded by the industry, while using current components and architectural approaches, system designers must add more discrete memory ICs to the line cards and/or add more embedded memory on the packet processor. This results in higher cost and power consumption, the use of more space on the line cards and additional communication interference between the ICs, which in turn results in additional bandwidth limitation problems.

We have developed our Bandwidth Engine and LineSpeed families of ICs to synergistically address the need for high-speed data access and throughput currently confronting networking system designers. We expect our IC products to meet the increasing demands placed on conventional memory technology used on the line cards in high-bandwidth networking systems. We believe that our products and technology are well positioned as replacements for existing IC solutions in order to meet the needs of the next-generation networking systems that will require a large number of packet lookups and to support aggregated rates greater than 100 Gbps.

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Our Approach

Our historical business was focused on the licensing of our proprietary 1T-SRAM and SerDes I/O technologies. We have leveraged our proprietary IP to design our IC products to create new IC products to help networking OEMs address the approaching bottleneck in system performance.

On-chip Functionality

A significant performance bottleneck in any network line card is the need to transfer data between discrete ICs. Many of these data-transfer operations are iterative in nature, requiring subsequent, back-to-back accesses of the memory IC by the processor IC. Our Bandwidth Engine ICs have an arithmetic logic unit, or ALU, which enables the Bandwidth Engine IC to perform mathematical operations on data. By moving certain processing functions from the processor IC to the Bandwidth Engine IC through the use of this embedded ALU, the number of I/O transactions is reduced and the processor IC is freed up to perform other networking or micro-processing functions.

High-Performance Interface

High-speed, efficient I/Os are critical building blocks to meet high data transfer rate requirements for communication between ICs on network line cards. We believe that current networking system requirements necessitate an industry transition from parallel I/O to serial I/O. As a result, semiconductor companies are increasingly turning to serial I/O architectures to achieve needed system performance. For example, high-performance ICs that are sold into wide markets, such as FPGAs and NPUs, are using serial I/Os to ensure they can match the performance of, and compete with ASICs. While SerDes I/Os provide significantly enhanced performance over parallel I/Os, SerDes I/Os have higher power consumption, which is a challenge for IC designers. Our SerDes I/Os are tuned for low power consumption to meet our customers' stringent power consumption requirements. Using serial I/O, IC developers also are able to reduce pin count (the wired electrical pins that connect an IC to the network line card on which it is mounted) on the IC. With reducing geometries, the size of most high-performance ICs is dictated by the number of pins required, rather than the amount of logic and memory embedded in the chip. As a result, using serial I/O facilitates cost reduction and reduced system power consumption, while improving the performance of both the IC itself and the overall system.

We make our I/O technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering their development and validation costs. Interoperability reduces development time, thereby reducing the overall time to market of our customers' ICs.

Analog Design Capabilities

We have invested in personnel needed to define, design and market high-performance analog IC products. We have built a team of experienced engineers who combine industry expertise with advanced semiconductor design expertise to meet customer requirements and develop new products to bring to market. We intend to leverage these capabilities to achieve new levels of integration, power reduction and performance, enabling our customers to achieve differentiation in their end systems.

GigaChip Interface Protocol

In addition to the physical characteristics of the serial I/O, the protocol used to transmit data is also an important element that impacts speed and performance. To address this and complement our Bandwidth Engine devices, we have developed the GigaChip Interface, or GCI, which is an open-interface transport protocol optimized for efficient chip-to-chip communications. The GCI

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electrical interface is compatible with the current industry standard (Common Electrical Interface, release #11, or CEI-11G-SR and XFI). GCI can enable highly efficient serial chip-to-chip communications, and its transport efficiency averages 90% for the data transfers it handles. GCI is included in our Bandwidth Engine ICs, and we are offering it to customers and prospective partners on terms intended to encourage widespread adoption.

High-Performance and High-Density Memory Architecture

The high-density of our proprietary 1T-SRAM technologies stems from the use of a single- transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM, or 6T-SRAM. Embedded memory utilizing our 1T-SRAM technologies typically provides speeds essentially equal to or greater than the speeds of traditional SRAM and DRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than embedded 6T-SRAM technology. Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generate less heat than traditional SRAM when operating at the same speed. This reduces system level heat dissipation and enables reliable operation using lower cost packaging.

Carrier and Enterprise Grade Quality and Reliability

Networking systems providers focused on the carrier and enterprise market have rigid performance and reliability standards that they require their IC vendors to achieve. Our Bandwidth Engine architecture and interface are designed for data robustness and employ end-to-end error checking and correction codes. Although the Bandwidth Engine functions as more than a discrete memory device, the onboard memory array represents a significant portion of the total chip area. Memory-dominated devices require substantially different and more robust testing than non-memory ICs in order to achieve the quality and reliability requirements of advanced networking systems. We have considered these requirements for our target customers and market segments and have incorporated design and manufacturing performance margins into our Bandwidth Engine IC products to accommodate them. As a result, production units of our Bandwidth Engine ICs have passed extensive reliability and life tests required for carrier and enterprise grade qualification certification.

Our Strategy

Our primary business objective is to be an IP-rich fabless semiconductor company offering ICs that deliver unparalleled bandwidth performance for next generation networking systems. The key components of the expansion of our strategic plan to become an IC supplier include the following strategies:

Target Large and Growing Markets

Our initial strategy is to target the multi-billion dollar networking and telecommunications OEM equipment market, and to date, we have secured approximately 40 design wins with networking and telecommunications OEMs. However, there is no assurance that these customer designs will be shipped in large volume by our customers to their customers. We are engaged with both existing customers and customer prospects, where we are working to achieve design wins, and we refer to these engagements as design-wins-in- progress.

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Leverage Technologies to Create New Products

Our strategy is to combine our proprietary IP and design and applications expertise to address the needs of several upcoming generations of advanced networking systems. We believe an IC combining our 1T-SRAM and serial I/O with logic, such as in an ALU, and other functions can provide a system-level solution and significantly improve overall system performance at lower cost while using less power. Another strategy is to leverage our high-speed serial I/O to create non-memory denominated ICs.

Expand Adoption of the GigaChip Interface Protocol

Our goal is for our GCI interface protocol to become an open industry standard that is designed into other ICs in the system, as we believe this will further enable serial communication on network line cards and encourage adoption of our Bandwidth Engine IC products. A number of IC providers have publicly announced their intention to support GCI, including the largest FPGA providers, Altera Corporation and Xilinx, Inc., with whom we work closely to support common customers. In addition, multiple networking systems companies, including actual and prospective customers, have adopted GCI.

Build Long-Term Relationships with Suppliers of Packet Processors

We believe that having long-term relationships with packet processor providers is critical to our success, as such relationships may enable us to reduce our time-to-market, provide us with a competitive advantage and expand our target markets. A key consideration of network system designers is to demonstrate interoperability between our Bandwidth Engine IC and the packet processors utilized in their systems. To obtain design wins for our Bandwidth Engine IC, we must demonstrate this interoperability, and also show that our IC works optimally with the packet processor to achieve the performance requirements. In addition, packet processor suppliers must adopt our GCI interface. To that end, we have been working closely with FPGA, ASIC and NPU providers, to enable interoperability between our Bandwidth Engine IC products and their high-performance products. To facilitate the acceptance of our Bandwidth Engine ICs, we have made available development and characterization kits for system designers to evaluate and develop code for next-generation networking systems. Our characterization kits are fully-functional hardware platforms that allow FPGA and ASIC providers, and their customers, to demonstrate interoperability of the Bandwidth Engine IC with the ASIC or FPGA the designers use within their networking systems.

Our Products

Bandwidth Engine

The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element. Our Bandwidth Engine ICs combine: (1) our proprietary high-density, high-speed, low latency embedded memory, (2) our high-speed serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM memory and serial I/O with logic and other intelligence functions provides a system-level solution and significantly improves overall system performance at lower cost, size and power consumption. Our Bandwidth Engine ICs can provide up to and over 4.5 billion memory accesses per second, which is more than twice the performance of current memory-based solutions. They also can enable system designers to significantly narrow the gap between processor and memory IC performance. Customers that design Bandwidth Engine ICs onto the line cards in their networking systems will re-architect their systems at the line-card level and use our

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product to replace traditional memory solutions. When compared with existing commercially available solutions, our Bandwidth Engine ICs may:

• provide up to four times the performance;

• reduce power by approximately 50%;

• reduce cost by greater than 50%; and

• result in a dramatic reduction in IC pin counts on the line card.

Our first generation Bandwidth Engine IC products contain 576 megabytes, or MB, of memory and use a serial I/O with up to 16 lanes operating at up to 10.3 Gbps per lane. Variations of this IC can have up to two interface ports, with up to eight serial receiver and eight serial transmitter lanes per port for a total of 16 lanes of 10.3 Gbps SerDes interface. These ICs include an ALU, which can perform read-modify-write operations. These ICs are tested to meet or exceed the standards for telecommunications carrier-class and enterprise-grade applications.

Our second generation Bandwidth Engine IC products contain 576 MB of memory and use serial I/O with up to 16 lanes operating at up to 15 Gbps per lane. In addition to a speed improvement of up to 50%, the architecture will enable several family member parts with added specialized features. To date, we have announced three unique devices in this product family:

• MSR620 with burst features optimized for oversubscription buffer applications;

• MSR720 with a write cache and memory coherency capability that allows for deterministic look ups optimized for state and que type applications; and

• MSR820 with increased intelligence for lookup, metering and statistics applications by adding dual counters, atomic and extensive metering functions.

We announced the architecture of our third generation Bandwidth Engine IC, which offers 800 Gbps I/O performance, up to 10 billion data accesses per second and 1 Gb of high access rate embedded 1T-SRAM memory. We expect to commence sampling this product in the second half of 2015.

The devices provide benefits of size, power, pin count and cost savings to our customers.

LineSpeed

Our first generation LineSpeed products consist of single-chip PHY ICs, including a 100G multi-mode gearbox and a 100G quad retimer. These devices are designed to support 10G, 40G and 100G standards for high-density line cards or modules for next generation ethernet and optical transport network applications. Built using standard CMOS technology, these devices are capable of supporting both short and long reach connections across different specifications.

In 2014, we introduced our LineSpeed 100G low power retimer, which is optimized for ultra low power consumption, integrated test features and small size. The low power retimer is primarily targeting opportunities in 100G CFP2, CFP4 and QSFP28 optical modules and active copper cables. We do not anticipate revenues from our LineSpeed ICs until 2016 or later.

IP Licensing and Distribution

Historically, we have offered our memory and I/O technologies on a worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies through product development, technology licensing and joint marketing relationships. We licensed our IP technology to semiconductor companies who incorporated our technology into ICs that they sold to their customers. As a result of the change in our corporate

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strategy, since early 2012, our IP licensing activities have been limited, and we expect this to continue. However, during 2014, 58% of our total revenues were generated from licensing and royalties related to our existing licensing arrangements, as we continue to perform and deliver under outstanding license agreements and collect royalties from 1T- SRAM licensees. To date, we have completed our performance obligations under our existing licensing agreements, and we expect licensing and royalty revenues to decline in 2015.

Research and Development

Our ability to compete in the future depends on successfully improving our technology to meet the market's increasing demand for higher performance and lower cost requirements. We have assembled a team of highly skilled engineers whose activities are focused on developing higher density, higher bandwidth, higher speed and lower cost next generation IC products. Development of our IC products requires the hiring of specialized chip design and product engineers, as well as significant fabrication and testing costs, including mask costs, as we bring these products to market. Our significant future research and development activities will include:

• designing next generation ICs with larger memory blocks and higher-speed SerDes;

• developing versions of our Bandwidth Engine ICs with alternative features, such as lower-speed SerDes, increased chip-level intelligence or smaller memory blocks to allow us to serve a broader range of applications and systems;

• developing versions of our LineSpeed ICs to meet customer demands, such as higher density, lower power and higher speeds;

• porting our 1T-SRAM and SerDes technology to more advanced foundry process nodes to support our IC development efforts; and

• developing new products that can leverage our proprietary IP portfolio and expand our market opportunity.

No development efforts are being dedicated to creating new or enhanced technology solely for use in licensing offerings.

Sales and Marketing

We believe that networking and communications systems OEMs typically prefer to extend the use of traditional memory solutions and their parallel interfaces, despite performance and costs challenges and are reluctant to change their technology platforms and adopt new designs and technologies, such as serial interfaces, which are an integral part of our product solutions. Therefore, our principal selling and marketing activities to date have been focused on persuading these OEMs and key component suppliers that our solutions provide critical performance advantages, as well as on securing design wins with them.

As of December 31, 2014, we had eight sales and marketing personnel managing and supporting our efforts to secure design wins for our IC products. Our sales and marketing personnel are located in the United States, Japan and China. We also have eight applications engineers who support our customer engagements and work closely with our engineering team on product definition. In addition to our direct sales team, we sell through sales representatives and distributors in the United States and Asia. We also have eight applications engineers who support our customer engagements and work closely with our engineering team on product definition. For our products, our applications engineers must engage with the customers' system architects and designers to propose our IC and IP, e.g., GCI Interface, solutions to address their systems' challenges. In the markets we serve, the time from initial customer engagement to design win to production volume shipments can range from two to three years. Networking and communications systems can have a product life from a few years to over 10 years.

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Our revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue. For the year ended December 31, 2014, Taiwan Semiconductor Manufacturing Co., Ltd., or TSMC, Kogent, Inc., our distributor, and Broadcom, represented 34%, 31% and 11% of total revenue, respectively. For the year ended December 31, 2013, TSMC and Broadcom, licensees of our memory IP, represented 41% and 13% of total revenue, respectively. For the year ended December 31, 2012, TSMC, Broadcom and Renesas Electronics Corporation, licensees of our memory IP, represented 28%, 26% and 12% of total revenue, respectively.

Customers in North America accounted for 28%, 30% and 41% of our revenues for the years ended December 31, 2014, 2013 and 2012, respectively. Customers in Japan accounted for 36%, 27% and 26% of our revenues for the years ended December 31, 2014, 2013 and 2012, respectively. Customers in Taiwan accounted for 35%, 42% and 28% of our revenues for the years ended December 31, 2014, 2013 and 2012, respectively. Our remaining revenues were from customers in the rest of Asia and in Europe.

Intellectual Property

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success, and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of December 31, 2014, we held approximately 68 U.S. and 22 foreign patents on various aspects of our technology, with expiration dates ranging from 2015 to 2031. We currently have approximately 40 pending patent applications in the U.S. and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

In December 2011, we sold 43 United States and 30 related foreign memory technology patents for $35 million in cash pursuant to a patent purchase agreement. Under the agreement, we retained a license to all of the sold patents that is unlimited with respect to our development, manufacturing and distribution of our Bandwidth Engine IC product line and any other proprietary products that we develop as long as they are not DRAM ICs. We also retained the rights necessary to renew existing 1T-SRAM licenses and to grant licenses similar in scope to identified foundries. We also retained rights to grant licenses for our second source purposes, to enable certain kinds of technology development and, to a limited extent, for certain ASIC products that incorporate one of our technology macros. However, the patent purchase agreement limits our rights to grant licenses under the sold patents outside the scope of our retained license and, in particular, limits the number of future licenses of 1T-SRAM memory technology that we can grant to developers of SoCs, which used to be the principal focus of our 1T-SRAM licensing activities.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, "Risk Factors."

Competition

The markets for our products are highly competitive. We believe that the principal competitive factors are:

• processing speed and performance;

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• density and cost;

• power consumption;

• reliability;

• interface requirements;

• ease with which technology can be customized for and incorporated into customers' products; and

• level of technical support provided.

We believe that we can compete favorably with respect to each of these criteria. Our proprietary 1T-SRAM embedded memory and high-speed serial I/O IP provides our Bandwidth Engine ICs with a competitive advantage over alternative devices. Alternative solutions are either DRAM or SRAM-based and can support either the memory size or speed requirements of high-performance networking systems, but generally not both. DRAM solutions provide a significant amount of memory at competitive cost, but DRAM solutions do not have the required fast access and cycle times to enable high-performance. The DRAM solutions currently used in networking systems include RLDRAM from Micron Technology, Inc., or Micron, and Integrated Silicon Solutions, Inc., LLDRAM from Renesas and DDR from Samsung Electronics Co., Ltd., Micron and others. In addition, Micron has announced a hybrid memory cube DRAM product, which consists of multiple DRAMs connected with a serial interface. SRAM solutions can meet high-speed performance requirements, but often lack adequate memory size. The SRAM solutions currently used in networking systems primarily include QDR or similar SRAM products from Cypress Semiconductor Corporation and GSI Technology, Inc. The majority of the currently available SRAM and DRAM solutions use a parallel, rather than a serial I/O. To offset these drawbacks, system designers generally use more discrete memory ICs, resulting in higher power consumption and greater utilization of space on the line card. Our competitors include established semiconductor companies with significantly longer operating histories, greater name recognition and reputation, large customer bases, dedicated manufacturing facilities and greater financial, technical, sales and marketing resources. This may allow them to respond more quickly than us to new or emerging technologies or changes in customer requirements. Many of our competitors also have significant influence in the semiconductor industry. They may be able to introduce new technologies or devote greater resources to the development, marketing and sales of their products than we can. Furthermore, in the event of a manufacturing capacity shortage, these competitors may be able to manufacture products when we are unable to do so.

Our Bandwidth Engine ICs compete with embedded memory solutions, stand-alone memory ICs, including both DRAM and SRAM ICs, and ASICs designed by customers in-house to meet their system requirements. Our prospective customers may be unwilling to adopt and design-in our ICs due to the uncertainties and risks surrounding designing a new IC into their systems and relying on a supplier that has limited history of manufacturing such ICs. In addition, Bandwidth Engine ICs require the customer and its other IC suppliers to implement our new chip-to-chip communication protocol, GCI. These parties may be unwilling to do this if they believe it could adversely impact their own future product developments or competitive advantages, or if they believe it might complicate their development process or increase the cost of their products. In order to remain competitive, we believe we must provide unparalleled memory IC solutions with the highest bandwidth capability for our target markets, which solutions are engineered and built for high-reliability carrier class and enterprise applications.

Our LineSpeed ICs compete with solutions offered by Applied Micro Circuits Corporation, Avago Technologies, Broadcom Corporation, Inphi Corporation, Semtech Corp., as well as other smaller analog signal processing companies. We may also compete with ASICs designed by customers in-house to meet their system requirements, as well as by optical module OEMs.

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Manufacturing

We depend on third-party vendors to manufacture, package, assemble and test our IC products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility for boards and system assembly. By outsourcing manufacturing, we are able to avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

We perform an ongoing review of product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meet design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers. We have achieved ISO 9001:2008 certification, and all of our manufacturing vendors have also achieved ISO 9001 certification.

Employees

As of December 31, 2014, we had 116 employees, consisting of 86 in research and development and engineering, 8 in sales and marketing, 11 in manufacturing operations and 11 in finance and administration. By location, we had 89 employees in the United States, 25 in our development center in India and 2 sales and marketing employees in Asia. We believe our future success depends, in part, on our ability to continue to attract and retain qualified technical and management personnel, particularly highly skilled design engineers involved in new product development, for which competition is intense. We believe that our employee relations are good.

Available Information

We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934 as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read and obtain copies of any materials we file with the SEC, at the SEC's Public Reference Room at 450 Fifth Street, NW, Washington, DC 20549. You can obtain additional information about the operation of the Public Reference Room by calling the SEC at 1.800.SEC.0330. In addition, the SEC maintains a website (www.sec.gov) that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Executive Officers

The names of our executive officers and certain information about them are set forth below:

Leonard Perham 71 President and Chief Executive Officer James W. Sullivan 46 Vice President of Finance and Chief Financial Officer Thomas Riordan 58 Chief Operating Officer and Executive Vice President John Monson 52 Vice President of Marketing and Sales

Leonard Perham, Mr. Perham was appointed President and Chief Executive Officer in November 2007. Mr. Perham was one of the original investors in MoSys and served on our Board of Directors from 1991 to 1997. In 2000, Mr. Perham retired from Integrated Device Technology, Inc., or IDT, where he served as Chief Executive Officer from 1991 and President and board member from 1986. From March 2000 to February 2012, Mr. Perham served as a member of or chairman of the

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board of directors of NetLogic Microsystems, a fabless semiconductor company. Prior to joining IDT, Mr. Perham was President and CEO of Optical Information Systems, Inc., a division of Exxon Enterprises. He was also a member of the founding team at Zilog, Inc. and held management positions at Advanced Micro Devices and Western Digital. Mr. Perham received a Bachelor of Science degree in Electrical Engineering from Northeastern University.

James W. Sullivan, Mr. Sullivan became our Vice President of Finance and Chief Financial Officer in January 2008. From July 2006 until January 2008, Mr. Sullivan served as Vice President of Finance and Chief Financial Officer at Apptera, Inc., a venture-backed company providing software for mobile advertising, search and commerce. From July 2002 until June 2006, Mr. Sullivan was the Chief Financial Officer at 8x8, Inc., a provider of voice over internet protocol communication services. Mr. Sullivan's prior experience includes various positions at 8x8, Inc. and PricewaterhouseCoopers LLP. He received a Bachelor of Science degree in Accounting from New York University and is a Certified Public Accountant.

Thomas Riordan, Mr. Riordan became our Chief Operating Officer and Executive Vice President in May 2011. Prior to joining the Company, Mr. Riordan was President and Chief Executive Officer of Exclara, a fabless semiconductor supplier of ICs for solid-state lighting from 2006 until 2010. From 2000 to 2004, Mr. Riordan served as Vice President of PMC-Sierra's microprocessor division. Mr. Riordan joined PMC-Sierra in August 2000 when it purchased Quantum Effects Devices, which he had co founded and served as President and Chief Executive Officer. Mr. Riordan serves on the board of directors of Mellanox Technologies. Mr. Riordan holds Bachelor of Science and Master of Science degrees in Electrical Engineering as well as a Bachelor of Arts degree in Government from the University of Central Florida and has done post-graduate work in Electrical Engineering at Stanford University.

John Monson, Mr. Monson became our Vice President of Marketing in February 2012. In early 2014, he assumed, on a permanent basis, additional responsibilities for our sales and business development activities and became our Vice President of Marketing and Sales. Prior to joining the Company, Mr. Monson was Vice President of Marketing for Mellanox Technologies, a supplier of interconnect solutions and services, from 2009 to 2012. From 2007 to 2008, Mr. Monson was Vice President of the EDC/PhyOptik business line at Inphi Corporation. He joined Inphi Corporation through business unit acquisition of Scintera Networks, where he was Vice President of Sales and Marketing from 2005 to 2007. Previously, he held various management positions at PMC-Sierra, Inc., Lucent Technologies and AT&T Microelectronics. Mr. Monson received a Bachelor of Science degree in Electrical Engineering from the University of Minnesota.

Overview

MoSys, Inc., together with its subsidiaries ("MoSys," the "Company," "we," "our" or "us"), is a fabless semiconductor company focused on the development and sale of integrated circuits, or ICs, for the high-speed networking, communications, storage and computing markets. Our technology delivers time-to-market, performance, power and economic benefits for system original equipment manufacturers, or OEMs. We have developed a family of ICs, called Bandwidth Engine, which combines our proprietary 1T-SRAM high-density embedded memory and high-speed 10 gigabits per second, or Gbps, and higher serial interface, or I/O, with our intelligent access technology and a highly efficient interface protocol. As the bandwidth requirements and amount of packet processing increase in high-speed networking systems, critical memory access bottlenecks can occur. Our Bandwidth Engine IC, with its combination of serial I/O, high-speed memory, and efficient, intelligent access, drastically increases memory accesses per second, removing these bottlenecks. In March 2013, we announced another IC product line under the LineSpeed product name. LineSpeed ICs are non-memory, high-speed SerDes I/O devices with gearbox and retimer functionality, which convert lanes of data received on line cards into different configurations and/or ensure signal integrity. These ICs are designed for next-generation ethernet and optical transport network applications. Historically, our primary business was the design, development, marketing, sale and support of differentiated intellectual property, or IP, including embedded memory and high-speed parallel and serial I/O used in advanced systems-on-chips, or SoCs. Currently, we are focused on developing differentiated IP-rich IC products and are dedicating substantially all of our research and development, marketing and sales budget to these IC products.

Our future success and ability to achieve and maintain profitability will be dependent on the marketing and sales of our IC products into networking, communications and other markets requiring high-bandwidth memory access. Since the beginning of 2010, we have invested an increasing amount of our research and development resources towards development of our ICs, and as of the end of 2012 had ceased our efforts to actively market our IP and establish license agreements for customers' new SoC development projects. However, we have made opportunistic sales of some of our IP. For instance, in December 2011, we sold a number of patents in an arrangement that provided $35 million

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in cash with no equity dilution to the Company and, in March 2012, we sold a portion of our SerDes technology and supporting workforce for approximately $4.3 million.

Due to the shift in our engineering and research and development focus and the decline in major consumer electronics applications utilizing customized versions of our 1T-SRAM technology, the competitiveness of, and demand for, our IP have declined since the beginning of 2011. While, we expect royalty revenue to continue to represent a significant portion of our revenues in 2014, albeit at a reduced level, we expect our revenue to transition to predominately IC product sales in 2014. To date, we have not generated significant revenue from sales of our IC products, and revenue from IP licensing and royalties represented the majority of our revenues for 2013. We are currently supporting existing design win customers and actively pursuing additional design wins for the use of our ICs in networking and communication equipment. We have established initial pricing of our IC products ordered to date, but longer-term volume prices will be subject to negotiations with our customers and may vary substantially from these initial prices.

Industry Background

The amount of data being transferred by networking, storage and computing systems is increasing rapidly, primarily driven by the growth of the Internet and demand for real-time processing of bandwidth intensive applications, such as video-on-demand, Internet protocol TV, peer-to-peer and cloud computing, web2.0 applications, 3G/4G wireless, voice-over-Internet protocol, and many others. In order to meet these demands, the network backbone, access, storage and data center infrastructure must scale in bandwidth and processing capability. In addition, system designers face the challenge of increasing the throughput of all subsystems for a variety of applications, such as video games, medical record and imaging transfers, and file sharing. These increased demands strain communication between onboard IC devices, limiting the data throughput in network switches and routers and the network backbone. To meet this demand, carrier and enterprise networks are undergoing significant changes and, most significantly, are migrating to packet-based Ethernet networks that enable higher throughput, lower cost and uniform technology across access, core and metro network infrastructure. These networks are now being designed to deliver voice, video and high-speed Internet access on one converged, efficient and flexible network. These trends require networking systems, especially the high-speed switches and routers that primarily comprise these networks, to comply with evolving market requirements and be capable of providing new services, better quality of service while supporting new protocols and standards. To support these trends, the next generations of networking systems must offer higher levels of packet forwarding rates, bandwidth density and be optimized to enable higher-density, lower power data path connectivity. This in turn necessitates new generations of packet processors and improved memory subsystems to enable system performance in support of these increased demands.

The OEM companies that produce networking and communications systems include Alcatel-Lucent, Brocade Communications Systems, Inc., Cisco Systems, Inc., Tel. LM Ericsson, Fujitsu Ltd., Hitachi Ltd., Huawei Technologies, Juniper Networks, Inc., Nokia Siemens Networks, and ZTE Corporation, as well as many other smaller suppliers. The networking and communications systems in the network backbone that must operate at higher speed and performance levels include the following types of routers, switches and other appliances: core, carrier Ethernet, edge, metro Ethernet, optical transport and service. In addition, networking and communications systems that sit on the edge of data centers, such as edge routers, aggregation switches and load-balancing and security appliances, must also operate at higher speed and performance levels. These networking and communications systems are typically built as a modular, multi-slot chassis that consists of several line cards with many network ports per line card or as a stand-alone, fixed configuration, flat frame containing multiple network line cards. These systems and their component line cards will generally need to support aggregate rates above 100 Gbps to meet the continued growth in network traffic. The type and number of semiconductors included on the line cards depend on the capacity, port type and target functionality of

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each card. Several types of semiconductors are included on each line card, including physical interface electronics, one or more packet processors and multiple memory chips. Packet processors are complex ICs developed using field programmable gate arrays, or FPGAs, application-specific integrated circuits, or ASICs, application specific standard products, or ASSPs, or network processing units, or NPUs, that perform high speed processing for functions, such as traffic shaping, metering, billing, statistics, detection and steering. Various types of memory ICs are used in order to facilitate the temporary storage and assist in the analysis and tracking of information embedded within each packet flowing through the processors. After a packet enters the line card through a physical interface, a packet or data processor helps separate the packet into smaller pieces for rapid analysis. Typically, the data is broken up into the packet header, which contains vital information on packet destination and type, such as the internet protocol address and payload, which contains the data being sent. In a basic operation, the packet header is stripped from the packet, and processed separately by the packet processing engine on the line card. The analysis of the packet header must occur at full data rates and typically requires accessing memory ICs many times. Simultaneously, the packet's payload, which may be substantially larger than the packet header, is also stored in memory ICs. Once processing is complete, the packet is re-combined to be sent from the system. Within the line card, communication between the packet processor and memory ICs occurs through either a parallel or serial interface. Combinations of physical pins on each type of chip are grouped together in a parallel or serial architecture to form a pathway, called a bus, through which information is transferred from one IC to the next.

Today, the majority of physical buses use a parallel architecture to communicate between processors and memory ICs, which means information can travel only in one direction and in one instance at a time. As processing speeds increase, in a parallel architecture the number of pins required and the speed of the bus become a limitation on system performance and capability. In a serial architecture, the number of connections is reduced substantially across fewer, higher-rate pins and data is transferred simultaneously in both directions. High speed serial bus architectures and more advanced I/O protocols must be supported by the various ICs included on the line card in order to remove the bottleneck and meet next generation bandwidth requirements.

The majority of networking systems sold and in operation today includes line cards that process data at speeds of 10 Gbps to 40 Gbps, supporting many aggregated slower ports. To accommodate the substantial and growing increase in demand for networking communications and applications, networking systems manufacturers are developing and bringing to market next-generation systems that run at aggregate speeds of 100 to 400 Gbps with plans to scale to thousands of Gbps, or Terabits, per second. Another major challenge to system designers is what we call the "memory performance barrier." Processor performance in applications such as computing and networking have continued to nearly double every 18 months, or even sooner, while the performance of memory technology has generally been able to double once every 10 years. Existing memory IC solutions based on parallel I/O architecture easily support speeds up to 40 Gbps, but are not optimal for meeting speeds of 100 Gbps and beyond due to system-level limitations for pin counts, power and performance. Traditional memory solutions currently used on line cards include both dynamic random access memory, or DRAM, and static random access memory, or SRAM, IC solutions. Line cards in networking systems use both specialized, high-performance DRAM ICs, such as reduced-latency DRAM, or RLDRAM, low-latency DRAM, or LLDRAM, and commodity DRAM, such as double data rate, or DDR ICs. In addition, networking systems use higher-performance SRAM ICs such as quad data rate, or QDR SRAM. Substantially all of these DRAM and SRAM memory ICs use parallel interfaces, which are slower than serial interfaces and will be challenged to meet the performance requirements of networking systems greater than 100 Gbps. The result is a gap between processor and memory performance. To meet the higher performance requirements being demanded by the industry, while using current components and architectural approaches, system designers must add more discrete memory ICs to the line cards and/or add more embedded memory on the packet processor. This results in higher cost and power

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consumption, the use of more space on the line cards and additional communication interference between the ICs, which in turn results in additional bandwidth limitation problems.

We have developed our Bandwidth Engine and LineSpeed family of ICs to synergistically address the need for high-speed data access and throughput currently confronting networking system designers. We expect our IC products to meet the increasing demands placed on conventional memory technology used on the line cards in high-bandwidth networking systems. We believe that our products and technology are well positioned as replacements for existing IC solutions in order to meet the needs of the next-generation networking systems that will require a large number of packet lookups and to support aggregated rates greater than 100 Gbps. However, we believe that networking and communications systems OEMs typically prefer to extend the use of traditional memory solutions and their parallel interfaces, despite performance and costs challenges and are reluctant to change their technology platforms and adopt new designs and technologies, such as serial interfaces, which are an integral part of our product solutions. Therefore, our principal selling and marketing activities to date have been focused on persuading these OEMs and key component suppliers that our solutions provide critical performance advantages, as well as on securing design wins with them. As of December 31, 2013, we had achieved approximately 20 such design wins, which we define as the point at which a customer has made a commitment to build a board against the fixed schematic for his system, and this board will utilize our ICs. However, there is no assurance that these customer designs will be shipped in volume production to their end customers.

Our Technology

Our historical business was focused on the licensing of our proprietary 1T-SRAM and SerDes I/O technologies. We leveraged our proprietary IP to design our IC products. The following discussion explains these technologies in further detail.

On-chip Functionality

A significant performance bottleneck in any network line card is the need to transfer data between discrete ICs. Many of these data-transfer operations are iterative in nature, requiring subsequent, back-to-back accesses of the memory IC by the processor IC. Our Bandwidth Engine ICs have an arithmetic logic unit, or ALU, which enables the Bandwidth Engine IC to perform mathematical operations on data. By moving certain processing functions from the processor IC to the Bandwidth Engine IC through the use of this embedded ALU, the number of I/O transactions is reduced and the processor IC is freed up to perform other networking or micro-processing functions.

High-Performance Interface

High-speed, efficient I/Os are critical building blocks to meet high data transfer rate requirements for communication between ICs on network line cards. We believe that current networking system requirements necessitate an industry transition from parallel I/O to serial I/O. As a result, semiconductor companies are increasingly turning to serial I/O architectures to achieve needed system performance. For example, high-performance ICs that are sold into wide markets, such as FPGAs and NPUs, are using serial I/Os to ensure they can match the performance of, and compete with ASICs. While SerDes I/Os provide significantly enhanced performance over parallel I/Os, SerDes I/Os have higher power consumption, which is a challenge for IC designers. Our SerDes I/Os are tuned for low-power consumption to meet our customers' stringent power consumption requirements. Using serial I/O, IC developers also are able to reduce pin count (the wired electrical pins that connect an IC to the network line card on which it is mounted) on the IC. With reducing geometries, the size of most high-performance ICs is dictated by the number of pins required, rather than the amount of logic and memory embedded in the chip. As a result, using serial I/O facilitates cost reduction and reduced

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system power consumption, while improving the performance of both the IC itself and the overall system.

We make our I/O technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering their development and validation costs. Interoperability reduces development time, thereby reducing the overall time to market of our customers' ICs.

Analog Design Capabilities

We have invested in personnel needed to define, design and market high-performance analog IC products. We have built a team of experienced engineers who combine industry expertise with advanced semiconductor design expertise to meet customer requirements and develop new products to bring to market. We intend to leverage these capabilities to achieve new levels of integration, power reduction and performance, enabling our customers to achieve differentiation in their end systems.

GigaChip Interface Protocol

In addition to the physical characteristics of the serial I/O, the protocol used to transmit data is also an important element that impacts speed and performance. To address this and complement our Bandwidth Engine devices, we have developed the GigaChip Interface, or GCI, which is an open-interface transport protocol optimized for efficient chip-to-chip communications. The GCI electrical interface is compatible with the current industry standard (Common Electrical Interface, release #11, or CEI-11). GCI can enable highly efficient serial chip-to-chip communications, and its transport efficiency averages 90% for the data transfers it handles. GCI is included in our Bandwidth Engine ICs, and we are offering it to customers and prospective partners on terms intended to encourage widespread adoption.

High-Performance and High-Density Memory Architecture

The high-density of our proprietary 1T-SRAM technologies stems from the use of a single- transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM, or 6T-SRAM. Embedded memory utilizing our 1T-SRAM technologies typically provides speeds essentially equal to or greater than the speeds of traditional SRAM and DRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than embedded 6T-SRAM technology. Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generate less heat than traditional SRAM when operating at the same speed. This reduces system level heat dissipation and enables reliable operation using lower cost packaging. The Bandwidth Engine uses our 1T-SRAM high-density memory technology to provide the density of DRAM and the speed of SRAM. The internal multi-bank memory array architecture used in our Bandwidth Engine ICs enables concurrent access operations. We believe that this architecture is also optimized for small algorithmic operations and data transfers, such as packet header analysis.

Carrier and Enterprise Grade Quality and Reliability

Networking systems providers focused on the carrier and enterprise market have rigid performance and reliability standards that they require their IC vendors to achieve. Our Bandwidth Engine architecture and interface are designed for data robustness and employ end-to-end error checking and correction codes. Although the Bandwidth Engine functions as more than a discrete memory device,

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the onboard memory array represents a significant portion of the total chip area. Memory-dominated devices require substantially different and more robust testing than non-memory ICs in order to achieve the quality and reliability requirements of advanced networking systems. We have considered these requirements for our target customers and market segments and have incorporated appropriate design and manufacturing performance margins into our Bandwidth Engine IC products. As a result, our first generation Bandwidth Engine ICs passed extensive reliability and life tests required for carrier and enterprise grade qualification certification as part of its release to production. To date, our second generation Bandwidth Engine ICs have substantially passed these tests, and we expect to achieve certification in the first half of 2014.

Our Strategy

Our primary business objective is to become an IP-rich fabless semiconductor company offering ICs that deliver unparalleled bandwidth performance for next generation networking systems. The key components of the expansion of our strategic plan to become an IC supplier include the following strategies:

Target Large and Growing Markets

Our initial strategy is to target the multi-billion dollar networking and telecommunications equipment market, and to date, we have secured multiple design wins with networking and telecommunications OEMs. We are engaged with both existing customers and customer prospects, where we are working to achieve design wins, and we refer to these engagements as design-wins-in-progress.

Leverage Technologies to Create New Products

Our strategy is to combine our proprietary IP and design and applications expertise to address the needs of several upcoming generations of advanced networking systems. We believe an IC combining our 1T-SRAM and serial I/O with logic, such as in an ALU, and other functions can provide a system-level solution and significantly improve overall system performance at lower cost while using less power. Another strategy is to leverage our high-speed serial I/O to create non-memory denominated ICs. To date, we have leveraged our serial I/O and analog design capabilities to bring our initial LineSpeed IC product family to market in 2013.

Expand Adoption of the GigaChip Interface Protocol

Our goal is for our GCI interface protocol to become an open industry standard that is designed into other ICs in the system, as we believe this will further enable serial communication on network line cards and encourage adoption of our Bandwidth Engine IC products. A number of IC providers have publicly announced their intention to support GCI, including the largest FPGA providers, Altera Corporation and Xilinx, Inc., with whom we work closely to support common customers. In addition, multiple networking systems companies, including actual and prospective customers, have adopted GCI.

Build Long-Term Relationships with Suppliers of Packet Processors

We believe that having long-term relationships with packet processor providers is critical to our success, as such relationships may enable us to reduce our time-to-market, provide us with a competitive advantage and expand our target markets. A key consideration of network system designers is to demonstrate interoperability between our Bandwidth Engine IC and the packet processors utilized in their systems. To obtain design wins for our Bandwidth Engine IC, we must demonstrate this interoperability, and also show that our IC works optimally with the packet processor to achieve the performance requirements. In addition, packet processor suppliers must adopt our GCI interface. To

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that end, we have been working closely with FPGA, ASIC and NPU providers, to enable interoperability between our Bandwidth Engine IC products and their high-performance products. To facilitate the acceptance of our Bandwidth Engine ICs, we have made available development and characterization kits for system designers to evaluate and develop code for next-generation networking systems. Our characterization kits are fully-functional hardware platforms that allow FPGA and ASIC providers, and their customers, to demonstrate interoperability of the Bandwidth Engine IC with the ASIC or FPGA the designers use within their networking systems.

Our Products

Bandwidth Engine

The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element. Our Bandwidth Engine ICs combine: (1) our proprietary high-density, high-speed, low latency embedded memory, (2) our high-speed serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM memory and serial I/O with logic and other intelligence functions provides a system-level solution and significantly improves overall system performance at lower cost, size and power consumption. Our Bandwidth Engine ICs can provide up to and over 4.5 billion accesses per second, which is more than twice the performance of current memory-based solutions. They also can enable system designers to significantly narrow the gap between processor and memory IC performance. Customers that design Bandwidth Engine ICs onto the line cards in their networking systems will re-architect their systems at the line card level and use our product to replace traditional memory solutions. When compared with existing commercially available solutions, our Bandwidth Engine ICs may:

•provide up to four times the performance;

•reduce power by approximately 50%;

•reduce cost by greater than 50%; and

•result in a dramatic reduction in IC pin counts on the line card.

The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element.

Our first generation Bandwidth Engine IC contains 576 megabytes, or MB, of memory and uses 10.3 Gbps SerDes I/O technology. Variations of this IC can have up to two interface ports, with up to eight serial receiver and eight serial transmitter lanes per port for a total of 16 lanes of 10.3 Gbps SerDes interface. These ICs include an ALU, which can perform read-modify-write operations. These ICs are tested to meet or exceed the standards for telecommunications carrier-class and enterprise-grade applications.

We brought our second generation Bandwidth Engine IC family of devices to market in 2013, and we began sampling these devices in mid-2013. These devices operate at up to 480 Gbps using sixteen 15 Gbps SerDes lanes. In addition to a speed improvement of up to 50%, the architecture will enable several family member parts with added specialized features. To date, we have announced three unique devices:

•MSR620 adds burst features optimized for oversubscription buffer applications;

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•MSR720 adds a write cache and memory coherency capability that allows for deterministic look ups optimized for state and que type applications; and

•MSR820 delivers increased intelligence for lookup, metering and statistics applications by adding dual counters, atomic and extensive metering functions.

The devices will represent a significant improvement in speed and features, supporting aggregate line rates of up to 400 Gbps and further reduce size, pin count and power.

LineSpeed

We brought our first generation of LineSpeed products to market and began sampling in 2013. Our first LineSpeed products consist of single-chip PHY ICs, including a 100G multi-mode gearbox and a 100G Quad retimer. These devices are designed to support 10G, 40G and 100G standards for high-density line cards or modules for next generation ethernet and optical transport network applications. Built using standard CMOS technology, these devices are capable of supporting both short and long reach connections across different specifications. We do not expect to generate significant revenue from our LineSpeed ICs until 2015 or later.

IP Licensing and Distribution

Historically, we have offered our memory and I/O technologies on a worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies through product development, technology licensing and joint marketing relationships. We licensed our IP technology to semiconductor companies who incorporated our technology into ICs that they sold to their customers. As a result of the change in our corporate strategy, since early 2012, our IP licensing activities have been limited, and we expect this to continue. We intend to avoid future licensing projects that require significant use of our engineering resources, as our engineering personnel are now focused on our IC products. However, during 2013, substantially all of our revenues were generated from licensing and royalties related to our existing licensing arrangements, as we continue to perform and deliver under outstanding license agreements and collect royalties from 1T-SRAM licensees. To date, we have substantially completed our performance obligations under our existing agreements, and we expect licensing and royalty revenues to decline in 2014.

Customers in North America accounted for 30%, 41% and 39% of our revenues for the years ended December 31, 2013, 2012 and 2011, respectively. Customers in Japan accounted for 27%, 26% and 33% of our revenues for the years ended December 31, 2013, 2012 and 2011, respectively. Customers in Taiwan accounted for 42%, 28% and 23% of our revenues for the years ended December 31, 2013, 2012 and 2011, respectively. Our remaining revenues were from customers in the rest of Asia and in Europe.

Research and Development

Our ability to compete in the future depends on successfully improving our technology to meet the market's increasing demand for higher performance and lower cost requirements. We have assembled a team of highly skilled engineers whose activities are focused on developing higher density, higher bandwidth, higher speed and lower cost next generation IC products. Development of our IC products requires the hiring of specialized chip design and product engineers, as well as significant fabrication and testing costs, including mask costs, as we bring these products to market. Our significant future research and development activities will include:

•designing next generation ICs with larger memory blocks and higher-speed SerDes;

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•developing versions of our Bandwidth Engine ICs with alternative features, such as lower-speed SerDes, increased intelligence or smaller memory blocks to allow us to serve a broader range of applications and systems;

•developing versions of our initial LineSpeed ICs to meet customer demands, such as lower power and higher speeds;

•porting our 1T-SRAM and SerDes technology to more advanced foundry process nodes to support our IC development efforts; and

•developing new products that can leverage our proprietary IP portfolio and expand our market opportunity.

No development efforts are being dedicated to creating new or enhanced technology solely for use in licensing offerings.

As of December 31, 2013, we employed 85 individuals in engineering and research and development, of which 23 were employed in our design center in Hyderabad, India. For the years ended December 31, 2013, 2012 and 2011, research and development expenditures totaled approximately $23.3 million, $28.5 million and $26.2 million, respectively.

Sales and Marketing

As of December 31, 2013, we had seven sales and marketing personnel managing and supporting our efforts to secure design wins for our IC products. Our sales and marketing personnel are located in the United States, Japan and China. In addition to our direct sales team, we sell through sales representatives and distributors in the United States and Asia. We also have 8 applications engineers who support our customer engagements and work closely with our engineering team on product definition. For our products, our applications engineers must engage with the customers' system architects and designers to propose our IC and IP, e.g., GCI Interface, solutions to address their systems' challenges. In the markets we serve, the time from initial customer engagement to design win to production volume shipments can range from two to three years. Networking and communications systems can have a product life from a few years to over 10 years.

Our IP revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue. For the year ended December 31, 2013, Taiwan Semiconductor Manufacturing Co., Ltd., or TSMC, and Broadcom, represented 41% and 13% of total revenue, respectively. For the year ended December 31, 2012, TSMC, Broadcom and Renesas, represented 28%, 26% and 12% of total revenue, respectively. For the year ended December 31, 2011, TSMC, Renesas and Broadcom represented 23%, 17% and 12% of total revenue, respectively.

Intellectual Property

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success, and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of December 31, 2013, we held approximately 71 U.S. and 16 foreign patents on various aspects of our technology, with expiration dates ranging from 2014 to 2031. We currently have approximately 51 pending patent applications in the U.S. and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

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In December 2011, we sold 43 United States and 30 related foreign memory technology patents for $35 million in cash pursuant to a patent purchase agreement. Under the agreement, we retained a license to all of the sold patents that is unlimited with respect to our development, manufacturing and distribution of our Bandwidth Engine IC product line and any other proprietary products that we develop as long as they are not DRAM ICs. We also retained the rights necessary to renew existing 1T-SRAM licenses and to grant licenses similar in scope to identified foundries. We also retained rights to grant licenses for our second source purposes, to enable certain kinds of technology development and, to a limited extent, for certain ASIC products that incorporate one of our technology macros. However, the patent purchase agreement limits our rights to grant licenses under the sold patents outside the scope of our retained license and, in particular, limits the number of future licenses of 1T-SRAM memory technology that we can grant to developers of SoCs, which used to be the principal focus of our 1T-SRAM licensing activities.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, "Risk Factors."

Competition

The markets for our products are highly competitive. We believe that the principal competitive factors are:

•processing speed and performance;

•density and cost;

•power consumption;

•reliability;

•interface requirements;

•ease with which technology can be customized for and incorporated into customers' products; and

•level of technical support provided.

We believe that we can compete favorably with respect to each of these criteria. Our proprietary 1T-SRAM embedded memory and high-speed serial I/O IP provides our Bandwidth Engine ICs with a competitive advantage over alternative devices. Alternative solutions are either DRAM or SRAM-based and can support either the memory size or speed requirements of high-performance networking systems, but generally not both. DRAM solutions provide a significant amount of memory at competitive cost, but DRAM solutions do not have the required fast access and cycle times to enable high-performance. The DRAM solutions currently used in networking systems include RLDRAM from Micron Technology, Inc., or Micron, and Integrated Silicon Solutions, Inc., LLDRAM from Renesas and DDR from Samsung Electronics Co., Ltd., Micron and others. In addition, Micron has announced a hybrid memory cube DRAM product, which consists of multiple DRAMs connected with a serial interface. SRAM solutions can meet high-speed performance requirements, but often lack adequate memory size. The SRAM solutions currently used in networking systems primarily include QDR or similar SRAM products from Cypress Semiconductor Corporation and GSI Technology, Inc. The majority of the currently available SRAM and DRAM solutions use a parallel, rather than a serial I/O. To offset these drawbacks, system designers generally use more discrete memory ICs, resulting in higher power consumption and greater utilization of space on the line card. Our competitors include

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established semiconductor companies with significantly longer operating histories, greater name recognition and reputation, large customer bases, dedicated manufacturing facilities and greater financial, technical, sales and marketing resources. This may allow them to respond more quickly than us to new or emerging technologies or changes in customer requirements. Many of our competitors also have significant influence in the semiconductor industry. They may be able to introduce new technologies or devote greater resources to the development, marketing and sales of their products than we can. Furthermore, in the event of a manufacturing capacity shortage, these competitors may be able to manufacture products when we are unable to do so.

Our Bandwidth Engine ICs compete with embedded memory solutions, stand-alone memory ICs, including both DRAM and SRAM ICs, and ASICs designed by customers in-house to meet their system requirements. Our prospective customers may be unwilling to adopt and design-in our ICs due to the uncertainties and risks surrounding designing a new IC into their systems and relying on a supplier that has almost no history of manufacturing such ICs. In addition, Bandwidth Engine ICs require the customer and its other IC suppliers to implement our new chip-to-chip communication protocol, GCI. These parties may be unwilling to do this if they believe it could adversely impact their own future product developments or competitive advantages, or if they believe it might complicate their development process or increase the cost of their products. In order to remain competitive, we believe we must provide unparalleled memory IC solutions with the highest bandwidth capability for our target markets, which solutions are engineered and built for high-reliability carrier class and enterprise applications.

Our LineSpeed ICs compete with solutions offered by Applied Micro Circuits Corporation, Avago Technologies, Broadcom, Inphi Corporation, Semtech Corp., as well as other smaller analog signal processing companies. We may also compete with ASICs designed by customers in-house to meet their system requirements, as well as by optical module OEMs.

Manufacturing

We depend on third-party vendors to manufacture, package, assemble and production test our IC products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility for boards and system assembly. By outsourcing manufacturing, we are able to avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

Quality Assurance. We perform an ongoing review of product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance meet design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers. We have achieved ISO 9001:2008 certification, and all of our manufacturing vendors have also achieved ISO 9001 certification.

Employees

As of December 31, 2013, we had 104 employees, consisting of 76 in research and development and engineering, 7 in sales and marketing, 9 in manufacturing operations and 12 in finance and administration. By location, we had 79 employees in the United States, 23 in our development center in India and 2 sales and marketing employees in Asia. We believe our future success depends, in part, on our ability to continue to attract and retain qualified technical and management personnel, particularly highly skilled design engineers involved in new product development, for which competition is intense. We believe that our employee relations are good.

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Available Information

We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934 as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read and obtain copies of any materials we file with the SEC, at the SEC's Public Reference Room at 450 Fifth Street, NW, Washington, DC 20549. You can obtain additional information about the operation of the Public Reference Room by calling the SEC at 1.800.SEC.0330. In addition, the SEC maintains a website (www.sec.gov) that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Executive Officers

The names of our executive officers and certain information about them are set forth below:

Leonard Perham 70 President and Chief Executive Officer James W. Sullivan 45 Vice President of Finance and Chief Financial Officer Thomas Riordan 57 Chief Operating Officer and Executive Vice President John Monson 51 Vice President of Marketing and Sales

Leonard Perham, Mr. Perham was appointed President and Chief Executive Officer in November 2007. Mr. Perham was one of the original investors in MoSys and served on our Board of Directors from 1991 to 1997. In 2000, Mr. Perham retired from Integrated Device Technology, Inc., or IDT, where he served as Chief Executive Officer from 1991 and President and board member from 1986. From March 2000 to February 2012, Mr. Perham served as a member of or chairman of the board of directors of NetLogic Microsystems, a fabless semiconductor company. Mr. Perham also has been a venture partner with AsiaTech Management, a venture capital firm. Prior to joining IDT, Mr. Perham was President and CEO of Optical Information Systems, Inc., a division of Exxon Enterprises. He was also a member of the founding team at Zilog, Inc. and held management positions at Advanced Micro Devices and Western Digital. Mr. Perham received a Bachelor of Science degree in Electrical Engineering from Northeastern University.

James W. Sullivan, Mr. Sullivan became our Vice President of Finance and Chief Financial Officer in January 2008. From July 2006 until January 2008, Mr. Sullivan served as Vice President of Finance and Chief Financial Officer at Apptera, Inc., a venture-backed company providing software for mobile advertising, search and commerce. From July 2002 until June 2006, Mr. Sullivan was the Chief Financial Officer at 8x8, Inc., a provider of voice over internet protocol communication services. Mr. Sullivan's prior experience includes various positions at 8x8, Inc. and PricewaterhouseCoopers LLP. He received a Bachelor of Science degree in Accounting from New York University and is a Certified Public Accountant.

Thomas Riordan, Mr. Riordan became our Chief Operating Officer and Executive Vice President in May 2011. Prior to joining the Company, Mr. Riordan was President and Chief Executive Officer of Exclara, a fabless semiconductor supplier of ICs for solid-state lighting from 2006 until 2010. From 2000 to 2004, Mr. Riordan served as Vice President of PMC-Sierra's microprocessor division. Mr. Riordan joined PMC-Sierra in August 2000 when it purchased Quantum Effects Devices, which he had co-founded and served as President and Chief Executive Officer. Mr. Riordan serves on the board of directors of Mellanox Technologies. Mr. Riordan holds Bachelor of Science and Master of Science

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degrees in Electrical Engineering as well as a Bachelor of Arts degree in Government from the University of Central Florida and has done post-graduate work in Electrical Engineering at Stanford University.

John Monson, Mr. Monson became our Vice President of Marketing in February 2012. In early 2014, he assumed, on a permanent basis, additional responsibilities for our sales and business development activities and became our Vice President of Marketing and Sales. Prior to joining the Company, Mr. Monson was Vice President of Marketing for Mellanox Technologies, a supplier of interconnect solutions and services, from 2009 to 2012. From 2007 to 2008, Mr. Monson was Vice President of the EDC/PhyOptik business line at Inphi Corporation. He joined Inphi Corporation through business unit acquisition of Scintera Networks, where he was Vice President of Sales and Marketing from 2005 to 2007. Previously, he held various management positions at PMC-Sierra, Inc., Lucent Technologies and AT&T Microelectronics. Mr. Monson received a Bachelor of Science degree in Electrical Engineering from the University of Minnesota.

Company Overview

MoSys, Inc., together with its subsidiaries ("MoSys," the "Company," "we," "our" or "us"), is a fabless semiconductor company focused on the development and sale of integrated circuits, or ICs, for the high-speed networking, communications, storage and computing markets. Our technology delivers time-to-market, performance, power and economic benefits for system original equipment manufacturers, or OEMs. We have developed a family of ICs, called Bandwidth Engine, that combines our proprietary 1T-SRAM high-density embedded memory and high-speed 10 Gigabits per second, or Gbps, serial interface, or I/O, with our intelligent access technology and a highly efficient interface protocol. As the bandwidth requirements and amount of packet processing increase in high-speed networking systems, critical memory access bottlenecks can occur. Our Bandwidth Engine IC, with its combination of serial I/O, high-speed memory, and efficient, intelligent access, drastically increases memory accesses per second, removing these bottlenecks. The first applications for our Bandwidth Engine IC are in networking and communications systems to enable next generation, high density 10 Gbps, 40 Gbps, 80 Gbps and higher solutions. Historically, our primary business was the design, development, marketing, sale and support of differentiated intellectual property, or IP, including embedded memory and high-speed parallel and serial I/O used in advanced systems-on-chips, or SoCs. We are focused on developing differentiated IP-rich IC products, such as the Bandwidth Engine, and are dedicating substantially all of our research and development, marketing and sales budget to these IC products.

Our future success and ability to achieve and maintain profitability will be dependent on the marketing and sales of our Bandwidth Engine IC products into networking, communications and other markets requiring high bandwidth memory access. Since the beginning of 2010, we have invested an increasing amount of our research and development resources towards development of our Bandwidth Engine family of ICs, and as of the end of 2012 had ceased our efforts to actively market our IP and establish license agreements for customers' new SoC development projects. However, we have made opportunistic sales of some of our IP. For instance, in December 2011, we sold a number of patents in an arrangement that provided $35 million in cash with no equity dilution to the Company and, in March 2012, we sold a portion of our SerDes technology and supporting workforce for approximately $4.3 million, of which we have received $3.6 million through December 2012.

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Due to the shift in our engineering and research and development focus and the decline in major consumer electronics applications utilizing customized versions of our 1T-SRAM technology, our competitiveness and the demand for our IP have declined since the beginning of 2011. Revenue from IP licensing and royalties did represent the majority of our revenues for 2012. We expect revenue from IP licensing and royalties to represent a significant portion of our revenues in 2013, although at a significantly reduced level. Our expectation is that our revenue will transition from primarily licensing and royalty to predominately IC product sales.

Industry Background

The amount of data being transferred by networking, storage and computing systems is increasing rapidly, primarily driven by the growth of the Internet and demand for real-time processing of bandwidth intensive applications, such as video-on-demand, Internet protocol TV, peer-to-peer and cloud computing, web2.0 applications, 3G and 4G wireless, voice-over-Internet protocol, and many others. In order to meet these demands, the network backbone, access, storage and data center infrastructure must scale in bandwidth and processing capability. In addition, system designers face the challenge of increasing the throughput of all subsystems for a variety of applications, such as video games, medical record and imaging transfers, and file sharing. These increased demands strain communication between onboard IC devices, limiting the data throughput in network switches and routers and the network backbone. To support this trend, the next generations of networking systems must offer higher levels of packet forwarding rates and bandwidth density. This in turn necessitates new generations of packet processors and improved memory subsystems to enable system performance in support of these increased demands.

Networking systems, such as routers and switches, contain network line cards. The type and number of semiconductors included on the line cards depend on the capacity, port type and target functionality of each card. Several types of semiconductors are included on each line card, including physical interface electronics, one or more packet processors and multiple memory chips. Packet processors are complex ICs developed using field programmable gate arrays, or FPGAs, application-specific integrated circuits, or ASICs, application specific standard products, or ASSPs, or network processing units, or NPUs, that perform high speed processing for functions, such as traffic shaping, metering, billing, statistics, detection and steering. Various types of memory ICs are used in order to facilitate the temporary storage and assist in the analysis and tracking of information embedded within each packet flowing through the processors. After a packet enters the line card through a physical interface, a packet or data processor helps separate the packet into smaller pieces for rapid analysis. Typically, the data is broken up into the packet header, which contains vital information on packet destination and type, such as the IP address, and the payload, which contains the data being sent. The packet header is stripped from the packet, stored in memory ICs and processed separately by a packet processing engine on the line card. The analysis of the packet header must occur at full data rates and typically requires accessing memory ICs many times. Simultaneously, the packet's payload, which may be substantially larger than the packet header, is also stored in memory ICs. Once processing is complete, the packet is re-combined to be sent from the system. Within the line card, communication between the packet processor and memory ICs occurs through either a parallel or serial interface. Combinations of physical pins on each type of chip are grouped together in a parallel or serial architecture to form a pathway, called a bus, through which information is transferred from one IC to the next.

Today, the majority of physical buses use a parallel architecture to communicate between processors and memory ICs, which means information can travel only in one direction and in one instance at a time. As processing speeds increase, in a parallel architecture the number of pins required and the speed of the bus become a limitation on system performance and capability. In a serial architecture, the number of connections is reduced substantially across fewer, higher-rate pins and data

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is transferred simultaneously in both directions. High speed serial bus architectures and more advanced I/O protocols must be supported by the various ICs included on the line card in order to remove the bottleneck and meet next generation bandwidth requirements.

The majority of networking systems sold today includes line cards that process data at speeds of 10 Gbps to 40Gbps, supporting many aggregated slower ports. To accommodate the substantial and growing increase in demand for networking communications and applications, networking equipment manufacturers are beginning to produce next-generation systems that run at aggregate speeds of 100 Gbps with plans to scale to thousands of Gbps, or Terabits, per second. Another major challenge to system designers is what we call the "memory performance barrier." Processor performance in applications such as computing and networking have continued to nearly double every 18 months, or even faster, while the performance of memory technology has generally been able to double once every 10 years. Existing memory IC solutions based on parallel I/O architecture easily support speeds up to 40 Gbps, but will struggle to meet speeds of 100 Gbps and beyond due to system-level limitations for pin counts, power and performance. Traditional memory solutions currently used on line cards include both dynamic random access memory, or DRAM, and static random access memory, or SRAM, IC solutions. Line cards in networking systems use both specialized, high-performance DRAM ICs, such as reduced-latency DRAM, or RLDRAM, low-latency DRAM, or LLDRAM, and commodity DRAM, such as double data rate, or DDR ICs. In addition, networking systems use higher-performance SRAM ICs such as quad data rate, or QDR SRAM. Substantially all of these DRAM and SRAM memory ICs use parallel interfaces, which are slower than serial interfaces and will be challenged to meet the performance requirements of networking systems greater than 40 Gbps. The result is a gap between processor and memory performance. To meet the higher performance requirements being demanded by the industry, while using current components and architectural approaches, system designers must add more discrete memory ICs to the line cards. This results in higher cost and power consumption, the use of more space on the line cards and additional communication interference between the ICs, which in turn results in additional bandwidth limitation problems.

To address the bandwidth limitations currently confronting networking system designers, we have developed our Bandwidth Engine family of ICs. We expect our Bandwidth Engine IC products to address the increasing demands placed on conventional memory technology used on the line cards in high-bandwidth networking systems. We believe that our product and technology is required as a replacement for existing memory IC solutions in order to meet the needs of the next-generation networking systems that will require a large number of packet lookups and to support aggregated rates greater than 100 Gbps.

Bandwidth Engine IC Products

Our Bandwidth Engine ICs combine: (1) our proprietary high-density, high-speed, low latency embedded memory, (2) our high-speed serial 10 Gbps serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM memory and serial I/O with logic and other intelligence functions provides a system-level solution and significantly improves overall system performance at lower cost, size and power consumption. Our first-generation Bandwidth Engine ICs can provide over two billion accesses per second, which is more than twice the performance of current memory-based solutions. They also can enable system designers to significantly narrow the gap between processor and memory IC performance. Customers that design Bandwidth Engine ICs onto the line cards in their networking systems will re-architect their systems at the line card level and use our product to replace traditional memory solutions. When compared with existing commercially available solutions, our Bandwidth Engine ICs may:

•provide up to four times the performance;

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•reduce power by approximately 50%;

•reduce cost by greater than 50%; and

•result in a dramatic reduction in IC pin counts on the line card.

The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element.

Our first generation Bandwidth Engine IC contains 576 megabytes, or MB, of memory and uses 10.3 Gbps SerDes I/O technology. Variations of this IC can have up to two interface ports, with up to eight serial receiver and eight serial transmitter lanes per port for a total of 16 lanes of 10.3 Gbps SerDes interface. These ICs include an arithmetic logic unit, or ALU, that can perform read-modify-write operations. These ICs are tested to meet or exceed the standards for telecommunications carrier class and enterprise grade applications.

Our second generation Bandwidth Engine IC family and architecture was announced in late 2012. These devices will operate at up to 480 Gbps using sixteen 15 Gbps SerDes lanes. In addition to a speed improvement of up to 50%, the architecture will enable several family member parts with added specialized features. To date, we have announced three devices:

•MSR620 adds burst features optimized for oversubscription buffer applications;

•MSR720 adds a write cache and memory coherency capability that allows for deterministic look ups optimized for state and que type applications; and

•MSR820 delivers increased intelligence for lookup, metering and statistics applications by adding dual counters, atomic and extensive metering functions.

The devices will represent a significant improvement in speed and features, supporting aggregate line rates of up to 400 Gbps and further reduce size, pin count and power. We expect to begin sampling these devices in mid-2013.

On-chip Functionality

A significant performance bottleneck in any network line card is the need to transfer data between discrete ICs. Many of these data-transfer operations are iterative in nature, requiring subsequent, back-to-back accesses of the memory IC by the processor IC. Our Bandwidth Engine ICs have an ALU, which enables the Bandwidth Engine IC to perform mathematical operations on data. By moving certain processing functions from the processor IC to the Bandwidth Engine IC through the use of this embedded ALU, the number of I/O transactions is reduced and the processor IC is freed up to perform other networking or micro-processing functions.

High-Performance Interface

High-speed, efficient I/Os are critical building blocks to meet high data transfer rate requirements for communication between ICs on network line cards. We believe that current networking equipment system requirements necessitate an industry transition from parallel I/O to serial I/O. As a result, semiconductor companies are increasingly turning to serial I/O architectures to achieve needed system performance. For example, high-performance ICs that are sold into wide markets, such as FPGAs and NPUs, are using serial I/Os to ensure they can match the performance of, and compete with ASICs. Using serial I/O, IC developers also are able to reduce pin count (the wired electrical pins that connect an IC to the network line card on which it is mounted) on the IC. With reducing geometries, the size of most high-performance ICs is dictated by the number of pins required, rather than the amount of

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logic and memory embedded in the chip. As a result, using serial I/O facilitates cost reduction and reduced system power consumption, while improving the performance of both the IC itself and the overall system.

GigaChip Interface Protocol

In addition to the physical characteristics of the serial I/O, the protocol used to transmit data is also an important element that impacts speed and performance. To address this and complement our Bandwidth Engine devices, we have developed the GigaChip Interface, or GCI, which is an open-interface transport protocol optimized for efficient chip-to-chip communications. The GCI electrical interface is compatible with the current industry standard (Common Electrical Interface, release #11 or CEI-11). GCI can enable highly efficient serial chip-to-chip communications, and its transport efficiency averages 90% for the data transfers it handles. GCI is included in our Bandwidth Engine ICs, and we are offering it to customers and prospective partners on terms intended to encourage widespread adoption.

High-Performance and High-Density Memory Architecture

The Bandwidth Engine uses our proprietary 1T-SRAM high-density memory technology to provide the density of DRAM and the speed of SRAM. The internal multi-bank memory array architecture used in our Bandwidth Engine ICs enables concurrent access operations. We believe that this architecture is also optimized for small algorithmic operations and data transfers, such as packet header analysis.

Carrier and Enterprise Grade Quality and Reliability

Networking equipment providers focused on the carrier and enterprise market have rigid performance and reliability standards that they require their IC vendors to achieve. Our Bandwidth Engine architecture and interface are designed for data robustness and employ end-to-end error checking and correction codes. Although the Bandwidth Engine functions as more than a discrete memory device, the onboard memory array represents a significant portion of the total chip area. Memory-dominated devices require substantially different and more robust testing than non-memory ICs in order to achieve the quality and reliability requirements of advanced networking systems. We have considered these requirements for our target customers and market segments and have incorporated appropriate design and manufacturing performance margins into our Bandwidth Engine IC products. As a result, our first generation Bandwidth Engine passed extensive reliability and life tests required for carrier grade qualification certification as part of its release to production.

Our Technology

Our historical business was focused on the licensing of our proprietary 1T-SRAM and SerDes I/O technologies. We leveraged our proprietary IP to design our Bandwidth Engine IC. The following discussion explains these technologies in further detail, as well as our historical licensing activities, which have generated substantially all of our revenues in 2012.

1T-SRAM

Our innovative 1T-SRAM technologies provide major advantages over a traditional SRAM in cell stability, memory density and power consumption, making it more economical for designers to incorporate large amounts of embedded memory in their designs. In addition, our 1T-SRAM technologies offer all the benefits of the traditional SRAM, such as low latency, high speed and the opportunity to use a simple interface. Our 1T-SRAM technologies can achieve these advantages while

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utilizing standard logic manufacturing processes and providing the simple, standard SRAM interface that designers are accustomed to.

High-Density

The high-density of our 1T-SRAM technologies stems from the use of a single- transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM, i.e., 6T-SRAM. Increased density enables manufacturers of electronic products, such as cellular phones, video game consoles and digital cameras and camcorders, to incorporate additional functionality into a single IC, generally a SoC, resulting in overall cost savings.

Low-power Consumption

Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generate less heat than traditional SRAM when operating at the same speed. This reduces system level heat dissipation and enables reliable operation using lower cost packaging.

High-speed

Embedded memory utilizing our 1T-SRAM technologies typically provides speeds essentially equal to or greater than the speeds of traditional SRAM and DRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than embedded 6T-SRAM technology.

SerDes (I/Os)

High-speed

To meet increasing system performance requirements, which in many cases are being driven by the growth in the Internet and the need to transmit data faster, systems are requiring both more memory and faster communication between ICs in a system. Our interface technology includes high-speed serial I/Os, called SerDes. Our SerDes technology allows for fast exchange of data between ICs in the system and can support data rates of 2.5 to 11 Gbps in a number of protocols, including XAUI, 10G KR and PCI Express (generations 1 to 3). We are developing next generation SerDes solutions, which we are targeting to achieve data rates of 15 Gbps and support advanced geometry nodes, such as 28 nanometers, primarily for use in our IC products.

Interoperability

We make our I/O technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering their development and validation costs. Interoperability reduces development time, thereby reducing the overall time to market of our licensees' ICs.

Low power

While SerDes I/Os provide significantly enhanced performance over parallel I/Os, SerDes I/Os have higher power consumption, which is a challenge for IC designers. Our SerDes I/Os are tuned for low-power consumption to meet our customers' stringent power consumption requirements.

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Our Strategy

Our primary business objective is to become an IP-rich fabless semiconductor company offering ICs that deliver unparalleled bandwidth performance for next generation networking systems. The key components of the expansion of our strategic plan to become an IC supplier include the following IC-focused strategies:

Target Large and Growing Markets

Our initial strategy is to target the multi-billion dollar networking and telecommunications equipment market, which includes OEM companies such as Alcatel-Lucent, Brocade Communications Systems, Inc., Cisco Systems, Inc., Tel. LM Ericsson, Fujitsu Ltd., Hitachi Ltd., Huawei Technologies, Juniper Networks, Inc., Nokia Siemens Networks, ZTE Corporation, and others. To date, we have secured two design wins with networking and telecommunications OEMs. A "design win" means that the customer has completed its prototype evaluation, frozen its line-card specification and informed us that its next generation systems will use our Bandwidth Engine IC. We are engaged with multiple other customers, where we are working to achieve design wins, and we refer to these engagements as design-wins-in-progress.

Leverage Technologies to Create New Products

Our strategy is to combine our proprietary IP and design and applications expertise to address the needs of several upcoming generations of advanced networking equipment. We believe an IC combining our 1T-SRAM and serial I/O with logic, such as in an ALU, and other functions can provide a system-level solution and significantly improve overall system performance at lower cost while using less power. We intend to develop a Bandwidth Engine product portfolio that can serve a wide range of system performance requirements and provide cost reduction options. In addition, we can provide customized IC solutions to customers using their proprietary technology and architecture, which would allow for improved communication between our Bandwidth Engine IC and the customer's packet processor.

Another strategy is to leverage our high-speed serial I/O to create non-memory denominated ICs, which will work alongside the Bandwidth Engine ICs on 100 Gbps and higher system solutions. This will provide our customers with a more complete solution, and possibly allow us to sell a chipset containing multiple MoSys ICs.

Expand Adoption of the GigaChip Interface Protocol

Our goal is for our GCI interface protocol to become an open industry standard that is designed into other ICs in the system, as we believe this will further enable serial communication on network line cards and encourage adoption of our Bandwidth Engine IC products. Since 2010, we have publicly announced the following IC providers that intend to support GCI: Altera Corporation, Avago Technologies, Inc., LSI, Inc., NetLogic Microsystems, Inc. (acquired by Broadcom Corporation, or Broadcom), Renesas Electronics Corporation, or Renesas, and Xilinx, Inc. In addition, multiple network equipment companies, including actual and prospective customers, have adopted GCI.

Build Long-Term Relationships with Suppliers of Packet Processors

A key consideration of network system designers is to demonstrate interoperability between our Bandwidth Engine IC and the packet processors utilized in their systems. To obtain design wins for our Bandwidth Engine IC, we must demonstrate this interoperability, and also show that our IC works optimally with the packet processor to achieve the performance requirements. In addition, packet processor suppliers must adopt our GCI interface. To that end, we have been working closely with FPGA, ASIC and NPU providers, to enable interoperability between our Bandwidth Engine IC products and their high-performance products. To facilitate the acceptance of our Bandwidth Engine

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ICs, we have made available development and characterization kits for system designers to evaluate and develop code for next-generation networking systems. Our characterization kits are fully-functional hardware platforms that allow FPGA and ASIC providers, and their customers, to demonstrate interoperability of the Bandwidth Engine IC with the ASIC or FPGA the designers use within their networking systems. As we engage with ASSP and NPU providers, we will be developing characterization kits to support their products as well. We believe that having long-term relationships with packet processor providers is critical to our success, as such relationships may enable us to speed our time-to-market, provide us with a competitive advantage and expand our target markets.

Licensing and Distribution Strategy for our IP

Historically, we have offered our memory and I/O technologies on a worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies through product development, technology licensing and joint marketing relationships. We licensed our IP technology to semiconductor companies who incorporated our technology into ICs that they sold to their customers. As a result of the change in our corporate strategy, beginning in 2012, our IP licensing activities have been limited and this is expected to continue. We intend to avoid future licensing projects that require significant use of our engineering resources, as our engineering personnel are now focused on our IC products. However, during 2012, substantially all of our revenues were generated from licensing and royalties related to our existing licensing arrangements, as we continue to perform and deliver under outstanding license agreements and collect royalties from 1T-SRAM licensees. To date, we have substantially completed our performance obligations under our existing agreements, and, as a result, we expect licensing revenues to decline in 2013.

Customers in the United States accounted for 41%, 39% and 38% of our revenues for the years ended December 31, 2012, 2011 and 2010, respectively. Customers in Japan accounted for 26%, 33% and 43% of our revenues for the years ended December 31, 2012, 2011 and 2010, respectively. Customers in Taiwan accounted for 28%, 23% and 18% of our revenues for the years ended December 31, 2012, 2011 and 2010, respectively. Our remaining revenues were from customers in the rest of Asia and in Europe.

Project Licenses

Historically, we formed product development and IP licensing relationships directly with semiconductor companies. In these relationships, the prospective licensee's implementation of our technologies typically included customized development. Usually, these relationships involved both engineering work to implement our technology in the specified product and licensing the technology for manufacture and sale of the product. Although the precise terms contained in our license agreements vary, they generally include licensing fees and development fees for customizations based on the achievement of specified development milestones and royalties. The vast majority of our contracts allow for milestone billings based on work performed. If we perform the contracted services, usually the licensee is obligated to pay the license fees even if the licensee cancels the project prior to completion. The agreements often also provide for the payment of additional contract fees if we provide engineering or manufacturing support services related to the manufacture of the product. Provisions in our memory license agreements generally require the payment of royalties to us based on the future sale or manufacture of products utilizing our technologies. Generally, our project licenses grant rights on a non-exclusive, non-transferable basis, limited to the use of our technology as modified for the project covered by the license agreement. Our license agreements generally have a fixed term and are subject to renewal. Each new project requires a separate agreement or an addendum to modify an existing agreement. We are not expecting to enter into similar kinds of projects in the future, as such licenses generally require significant engineering effort and support.

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Technology Licenses

Historically, we also offered our technology to semiconductor companies and foundries through 1T-SRAM and I/O technology license agreements, under which we granted the licensee the additional right to create and modify designs to offer to its own customers or use internally. The contract fees associated with these arrangements typically require the licensee to pay us to port our technology to the licensee's manufacturing process and develop a template design that the licensee will be able to use to generate future designs. These agreements also may obligate the licensee to pay contract fees upon the achievement of specified development milestones and may provide for the payment of additional contract fees for engineering or manufacturing support services. Our memory technology license agreements include royalty provisions based on the sale or manufacture of products utilizing our technologies. The technology licenses are non-transferable and authorize the licensee to modify designs for its customers or internal use from the template design that we provide under the agreement. Typically, the template design applies only to a specified manufacturing process generation or specific application. The licensee may add future process generations or uses to the license agreement for additional contract fees.

Research and Development

Our ability to compete in the future depends on successfully improving our technology to meet the market's increasing demand for higher performance and lower cost requirements. We have assembled a team of highly skilled engineers whose activities are focused on developing higher density, higher bandwidth, higher speed and lower cost next generation IC products. Development of our Bandwidth Engine IC products requires the hiring of specialized chip design and product engineers, as well as significant fabrication and testing costs, including mask costs, as we bring these products to market. Our significant future research and development activities will include:

•designing next generation ICs with larger memory blocks and higher-speed SerDes;

•developing versions of our initial Bandwidth Engine IC with alternative features, such as lower-speed SerDes, increased intelligence or smaller memory blocks to allow us to serve a broader range of applications and systems;

•porting our 1T-SRAM and SerDes technology to more advanced foundry process nodes; and

•developing new products that can leverage our proprietary IP portfolio and expand our market opportunity.

No development efforts are being dedicated to creating new or enhanced technology solely for use in licensing offerings.

As of December 31, 2012, we employed 76 individuals in engineering and research and development, of which 17 were employed in our design center in Hyderabad, India. For the years ended December 31, 2012, 2011 and 2010, research and development expenditures totaled approximately $28.5 million, $26.2 million and $25.5 million, respectively.

Sales and Marketing

As of December 31, 2012, we had 7 sales and marketing personnel managing and supporting our efforts to secure design wins for our IC products. Our sales and marketing personnel are located in the United States, Japan and China. In addition to our direct sales team, we sell our technologies through sales representatives and distributors in the United States and Asia.

Our IP revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue. For the year ended December 31, 2012, Taiwan Semiconductor Manufacturing Co., Ltd., or TSMC, Broadcom and Renesas, represented 28%, 26% and 12% of total revenue, respectively. For the year ended December 31, 2011, TSMC, Renesas, and Broadcom represented 23%, 17% and 12% of total revenue, respectively. For the year ended December 31, 2010, Renesas, TSMC and Rohm Co., Ltd. represented 23%, 18% and 15% of total revenue, respectively.

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Intellectual Property

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success, and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of December 31, 2012, we held approximately 70 U.S. and 35 foreign patents on various aspects of our technology, with expiration dates ranging from 2013 to 2031. We currently have approximately 80 pending patent applications in the U.S. and abroad. There can be no assurance that others will not independently develop or patent similar or competing technology or design around any patents that may be issued to us, or that we will be able to successfully enforce our patents against infringement by others.

In December 2011, we sold 43 United States and 30 related foreign memory technology patents for $35 million in cash pursuant to a patent purchase agreement. Under the agreement, we retained a license to all of the sold patents that is unlimited with respect to our development, manufacturing and distribution of our Bandwidth Engine IC product line and any other proprietary products that we develop as long as they are not DRAM ICs. We also retained the rights necessary to renew existing 1T-SRAM licenses and to grant licenses similar in scope to identified foundries. We also retained rights to grant licenses for our second source purposes, to enable certain kinds of technology development and to a limited extent, for certain ASIC products that incorporate one of our technology macros. However, the patent purchase agreement limits our rights to grant licenses under the sold patents outside the scope of our retained license and, in particular, limits the number of future licenses of 1T-SRAM memory technology that we can grant to developers of SoCs, which used to be the principal focus of our 1T-SRAM licensing activities.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights and our ability to make, use, import, offer to sell, and sell products free from the intellectual property rights of others are subject to a number of factors, particularly those described in Part I, Item 1A, "Risk Factors."

Competition

The markets for our Bandwidth Engine IC products are highly competitive. We believe that the principal competitive factors are:

•processing speed and performance;

•density and cost;

•low-power consumption;

•reliability;

•interface requirements;

•ease with which technology can be customized for and incorporated into customers' products; and

•level of technical support provided.

We believe that we can compete favorably with respect to each of these criteria. Using our proprietary 1T-SRAM embedded memory and high-speed serial I/O IP provides our Bandwidth Engine ICs with a competitive advantage over alternative devices. Alternative solutions are either DRAM or SRAM-based and can support either the memory size or speed requirements of high-performance

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networking systems, but generally not both. DRAM solutions provide a significant amount of memory at competitive cost, but DRAM solutions do not have the required fast access and cycle times to enable high-performance. The DRAM solutions currently used in networking systems include RLDRAM from Micron Technology, Inc. and Integrated Silicon Solutions, Inc., LLDRAM from Renesas and DDR from Samsung Electronics Co., Ltd., or Samsung, Micron and others. SRAM solutions can meet high-speed performance requirements, but often lack adequate memory size. The SRAM solutions currently used in networking systems primarily include QDR or similar SRAM products from Cypress Semiconductor Corporation, GSI Technology, Inc. and Samsung. The majority of the currently available SRAM and DRAM solutions use a parallel, rather than a serial I/O. To offset these drawbacks, system designers generally use more discrete memory ICs, resulting in higher power consumption and greater utilization of space on the line card. Our competitors include established semiconductor companies with significantly longer operating histories, greater name recognition and reputation, large customer bases, dedicated manufacturing facilities and greater financial, technical, sales and marketing resources. This may allow them to respond more quickly than us to new or emerging technologies or changes in customer requirements. Many of our competitors also have significant influence in the semiconductor industry. They may be able to introduce new technologies or devote greater resources to the development, marketing and sales of their products than we can. Furthermore, in the event of a manufacturing capacity shortage, these competitors may be able to manufacture products when we are unable to do so.

Our Bandwidth Engine ICs compete with embedded memory solutions, stand-alone memory ICs, including both DRAM and SRAM ICs, and ASICs designed by customers in-house to meet their system requirements. Our prospective customers may be unwilling to adopt and design-in our ICs due to the uncertainties and risks surrounding designing a new IC into their systems and relying on a supplier that has almost no history of manufacturing such ICs. In addition, Bandwidth Engine ICs require the customer and its other IC suppliers to implement our new chip-to-chip communication protocol, GCI. These parties may be unwilling to do this if they believe it could adversely impact their own future product developments or competitive advantages, or if they believe it might complicate their development process or increase the cost of their products. In order to remain competitive, we believe we must provide unparalleled memory IC solutions with the highest bandwidth capability for our target markets, which solutions are engineered and built for high-reliability carrier class and enterprise applications.

Manufacturing

We depend on third-party vendors to manufacture, package, assemble and production test our Bandwidth Engine IC products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility for boards and system assembly. By outsourcing manufacturing, we are able to avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

Manufacturing and Testing. We use TSMC to manufacture and ASE, Inc. and Evans Analytical Group, LLC, or EAG, to assemble, package and production test, our IC products. We utilize eSilicon Corporation to assist with the management and support of certain of our manufacturing and testing operations.

Quality Assurance. We maintain an ongoing review of product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance exceeds the design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers.

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Employees

As of December 31, 2012, we had 95 employees, consisting of 76 in research and development and engineering, 7 in sales and marketing and 12 in finance and administration. By location, we had 76 employees in the United States, 17 in our development center in India and 2 sales and marketing employees in Asia. We believe our future success depends, in part, on our ability to continue to attract and retain qualified technical and management personnel, particularly highly skilled design engineers involved in new product development, for which competition is intense. We believe that our employee relations are good.

Available Information

We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934 as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read and copy any materials we file with the SEC, at the SEC's Public Reference Room at 450 Fifth Street, NW, Washington, DC 20549. You can obtain additional information about the operation of the Public Reference Room by calling the SEC at 1.800.SEC.0330. In addition, the SEC maintains a website (www.sec.gov) that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Executive Officers

The names of our executive officers and certain information about them are set forth below:

Leonard Perham 69 President and Chief Executive Officer James W. Sullivan 44 Vice President of Finance and Chief Financial Officer Thomas Riordan 56 Chief Operating Officer and Executive Vice President

Leonard Perham, Mr. Perham was appointed President and Chief Executive Officer in November 2007. Mr. Perham was one of the original investors in MoSys and served on our Board of Directors from 1991 to 1997. In 2000, Mr. Perham retired from Integrated Device Technology, Inc., or IDT, where he served as Chief Executive Officer from 1991 and President and board member from 1986. From March 2000 to February 2012, Mr. Perham served as a member of or chairman of the board of directors of NetLogic Microsystems, a fabless semiconductor company. Mr. Perham also has been a venture partner with AsiaTech Management, a venture capital firm. Prior to joining IDT, Mr. Perham was President and CEO of Optical Information Systems, Inc., a division of Exxon Enterprises. He was also a member of the founding team at Zilog, Inc. and held management positions at Advanced Micro Devices and Western Digital. Mr. Perham received a Bachelor of Science degree in Electrical Engineering from Northeastern University.

James W. Sullivan, Mr. Sullivan became our Vice President of Finance and Chief Financial Officer in January 2008. From July 2006 until January 2008, Mr. Sullivan served as Vice President of Finance and Chief Financial Officer at Apptera, Inc., a venture-backed company providing software for mobile advertising, search and commerce. From July 2002 until June 2006, Mr. Sullivan was the Chief Financial Officer at 8x8, Inc., a provider of voice over internet protocol communication services. Mr. Sullivan's prior experience includes various positions at 8x8, Inc. and PricewaterhouseCoopers LLP.

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He received a Bachelor of Science degree in Accounting from New York University and is a Certified Public Accountant.

Thomas Riordan, Mr. Riordan became our Chief Operating Officer and Executive Vice President in May 2011. Prior to joining the Company, Mr. Riordan was President and Chief Executive Officer of Exclara, a fabless semiconductor supplier of ICs for solid-state lighting from 2006 until 2010. From 2000 to 2004, Mr. Riordan served as Vice President of PMC-Sierra's microprocessor division. Mr. Riordan joined PMC-Sierra in August 2000 when it purchased Quantum Effects Devices, which he had co-founded and served as President and Chief Executive Officer. Mr. Riordan serves on the board of directors of Mellanox Technologies and PLX Technology. Mr. Riordan holds Bachelor of Science and Master of Science degrees in Electrical Engineering as well as a Bachelor of Arts degree in Government from the University of Central Florida and has done post-graduate work in Electrical Engineering at Stanford University.

Company Overview

MoSys, Inc., together with its subsidiaries ("MoSys," the "Company," "we," "our" or "us"), is a fabless semiconductor company focused on the development and sale of integrated circuits, or ICs, and intellectual property, or IP, for the high-speed networking, communications, storage and computing markets. Our technology delivers time-to-market, performance, power and economic benefits for system original equipment manufacturers, or OEMs, and technology licensees. We have developed a family of ICs, called Bandwidth Engine, which combines our proprietary 1T-SRAM high-density embedded memory and high-speed 10 Gigabits per second, or Gbps, serial interface, or I/O, with our intelligent access technology and a highly efficient interface protocol. As the bandwidth requirements and amount of packet processing increase in high-speed networking systems, critical memory access bottlenecks occur. Our Bandwidth Engine IC with its combination of serial I/O, high-speed memory, and efficient, intelligent access drastically increases memory accesses per second, removing these bottlenecks. The first applications for our Bandwidth Engine IC are in networking and communications systems to enable next generation, high density 10 Gbps, 40 Gbps and 100 Gbps solutions. Historically, our primary business has been the design, development, marketing, sale and support of differentiated IP including embedded memory and high-speed parallel and serial I/O used in advanced systems-on-chips, or SoCs. We plan to focus on differentiated IP-rich IC products, such as the Bandwidth Engine, and are dedicating an increasing amount of our R&D, marketing and sales budget to these products.

Since the beginning of 2010, we have invested an increasing amount of our research and development resources towards development of our Bandwidth Engine family of ICs. Our future success and ability to achieve and maintain profitability will be dependent on the marketing and sales of our Bandwidth Engine IC products into networking, communications and other markets requiring high bandwidth memory access. As a result, during 2011, we began placing less emphasis on IP licensing and deploying more resources towards our IC product development and marketing efforts. In December 2011, we sold a number of patents in an arrangement that provided $35 million in cash with no equity dilution to the Company. We intend to use the proceeds from this sale to partially fund our investment in our Bandwidth Engine IC product line. The transaction did not include any of the patents that cover our Bandwidth Engine IC product line, and we retained a license to the sold patents in order to execute current business with our IP technology customers and partners. However, the

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retained license limits, among other things, the number of future licenses of 1T-SRAM memory technology that we can grant to developers of SoCs, which, at one time, was a principal focus of our 1T-SRAM licensing activities. We still maintain a large patent portfolio with over 100 patents granted and more in process.

We expect revenue from IP licensing and royalties to continue to represent the majority of our revenues in 2012. Our expectation is that our revenue will transition from primarily licensing and royalty to predominately IC product sales over the next two years. Due to the shift in our engineering and research and development focus and the decline in major consumer electronics applications utilizing customized versions of our 1T-SRAM technology, our competitiveness and the demand for our IP have declined since the beginning of 2011. As a result of our reduced licensing activities, we expect our licensing and royalty revenue to decrease in future periods. We do not expect to generate significant revenue from our Bandwidth Engine ICs until the second half of 2012, or later, and believe that IC revenues are unlikely to match or exceed revenues generated from licensing and royalties in 2011 until at least 2013, if at all.

Industry Background

The amount of data being transferred by networking, storage and computing systems is increasing rapidly, primarily driven by the growth of the Internet and demand for real-time processing of bandwidth intensive applications, such as video-on-demand, Internet protocol TV, peer-to-peer and cloud computing, web2.0 applications, 3G and 4G wireless, voice-over-Internet protocol, and many others. In order to meet these demands, the network backbone, access, storage and data center infrastructure must scale in bandwidth and processing capability. In addition, system designers face the challenge of increasing the throughput of all subsystems for a variety of applications, including video games, medical record and imaging transfers, and file sharing. These increased demands strain communication between onboard IC devices, limiting the data throughput in network switches and routers and the network backbone. To support this trend, the next generations of networking systems must offer new levels of packet forwarding rates and bandwidth density. This in turn necessitates new generations of packet processors and improved memory subsystems to enable system performance in support of these increased demands.

Networking systems, such as routers and switches, contain network line cards. The type and number of semiconductors included on the line cards depend on the capacity, port type and target functionality of each card. Several types of semiconductors are included on each line card, including physical interface electronics, one or more packet processors and multiple memory chips. Packet processors are complex ICs developed using field programmable gate arrays, or FPGAs, application-specific integrated circuits, or ASICs, or network processing units, or NPUs, that perform high speed processing for functions, such as traffic shaping, metering, billing, statistics, detection and steering. Various types of memory ICs are used in order to facilitate the temporary storage of information embedded within each packet flowing through the processors. After a packet enters the line card through a physical interface, a packet or data processor helps separate the packet into smaller pieces for rapid analysis. Typically, the data is broken up into the packet header, which contains vital information on packet destination and type, such as the IP address, and the payload which contains the data being sent. The packet header is stripped from the packet, stored in memory ICs and processed separately by a packet processing engine on the line card. The analysis of the packet header must occur at full data rates and typically requires accessing the memory ICs multiple times. Simultaneously, the packet's payload, which may be substantially larger than the packet header, is also stored in memory ICs. The specific payload data may or may not be analyzed depending on the functionality of the line card. Once processing is complete, the packet is re-combined to be sent from the system. Within the line card, communication between the packet processor and memory ICs occurs through either a parallel or serial interface. Combinations of physical pins on each type of chip are grouped together in

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a parallel or serial architecture to form a pathway, called a bus, through which information is transferred from one IC to the next. Today, the majority of physical buses use a parallel architecture to communicate between processors and memory ICs, which means information can travel only in one direction and in one instance at a time. As processing speeds increase, in a parallel architecture the number of pins required and the speed of the bus become a limitation on system performance and capability. In a serial architecture, high speed serial bus architectures and more advanced I/O protocols will need to be supported by the various ICs included on the line card in order to remove the bottleneck and meet next generation bandwidth requirements.

The majority of networking systems sold today include line cards that process data at speeds of 10 Gbps, but to accommodate the substantial and growing increase in demand for networking communications and applications, networking equipment companies are beginning to produce next-generation systems that run at aggregate speeds of 40 Gbps up to hundreds of Gbps. Another major challenge to system designers is what we call the "memory performance barrier." Processor performance in applications such as computing and networking have continued to nearly double every 18 months, or even faster, while the performance of memory technology has generally been able to double once every 10 years. Existing memory IC solutions based on parallel I/O architecture easily support speeds of 10 Gbps, but will struggle to meet speeds of 40 Gbps and beyond due to system-level limitations for pin counts, power and performance. Traditional memory solutions currently used on line cards include both dynamic random access memory, or DRAM, and static random access memory, or SRAM, IC solutions. Line cards in networking systems use both specialized, high-performance DRAM ICs, such as reduced-latency DRAM, or RLDRAM, low-latency DRAM, or LLDRAM, and commodity DRAM, such as double data rate, or DDR ICs. In addition, networking systems use higher-performance SRAM ICs such as quad data rate, or QDR SRAM. Substantially all of these DRAM and SRAM memory ICs use parallel interfaces, which are slower than serial interfaces and will be challenged to meet the performance requirements of networking systems greater than 40 Gbps. To meet the higher performance requirements being demanded by the industry, while using current components and architectural approaches, system designers must add more discrete memory ICs to the line cards. This results in higher cost and power consumption, the use of more space on the line cards and additional communication interference between the ICs, which results in additional bandwidth limitation problems.

To address the bandwidth limitations currently confronting networking system designers, we have developed our Bandwidth Engine family of ICs. We expect our Bandwidth Engine IC products to address the increasing demands placed on conventional memory technology used on the line cards in high-bandwidth networking systems. We believe that our product and technology is required as a replacement of existing memory IC solutions in order to meet the needs of the next-generation networking systems that require large number of packet lookups and run at speeds greater than 40 Gbps.

Bandwidth Engine IC Product

Our Bandwidth Engine IC combines: (1) our proprietary 1T-SRAM high-density, high-speed, low latency embedded memory, (2) our high-speed serial 10 Gbps serial interface technology, or SerDes, (3) an open-standard interface protocol and (4) intelligent access technology. We believe an IC combining our 1T-SRAM and serial I/O with logic and other functions provides a system-level solution and significantly improves overall system performance at lower cost and power consumption. Our Bandwidth Engine ICs can provide over two billion accesses per second, over twice the performance of current memory-based solutions, and enable system designers to significantly narrow the gap between processor and memory IC performance. Customers that design Bandwidth Engine ICs onto the line cards in their networking systems will re-architect their systems at the line card level and use our

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product to replace traditional memory solutions. When compared with existing commercially available solutions, our Bandwidth Engine ICs may—

•increase performance up to four times;

•reduce power by approximately 50%;

•reduce cost by greater than 50%; and

•result in a dramatic reduction in IC pin counts on the line card.

The Bandwidth Engine is a memory-dominated IC that has been designed to be a high-performance companion IC to packet processors. While the Bandwidth Engine primarily functions as a memory device with a high-performance and high-efficiency interface, it also can accelerate certain processing operations by serving as a co-processor element.

Our first generation Bandwidth Engine IC contains 576 megabytes, or MB, of 1T-SRAM memory and uses 10.3 Gbps SerDes I/O technology. Variations of this IC can have up to two interface ports, with up to 8 serial receiver and 8 serial transmitter lanes per port for a total of 16 lanes of 10.3 Gbps SerDes interface. These ICs include an arithmetic logic unit, or ALU, that can perform read-modify-write operations. These ICs are tested to meet or exceed the standards for telecommunications carrier class and enterprise grade applications.

On-chip Functionality

A significant performance bottleneck in any network line card is the need to transfer data between discrete ICs. Many of these data-transfer operations are iterative in nature, requiring subsequent, back-to-back accesses of the memory IC by the processor IC. Our Bandwidth Engine ICs have an ALU, which enables the Bandwidth Engine IC to perform mathematical operations on data. By moving certain processing functions from the processor IC to the Bandwidth Engine IC through the use of this embedded ALU, the number of I/O transactions is reduced and the processor IC is freed up to perform other networking or micro-processing functions.

High-Performance Interface

High speed, efficient I/Os are critical building blocks to meet high data transfer rate requirements for communication between ICs on network line cards. We believe that current networking equipment system requirements necessitate an industry transition from parallel I/O to serial I/O. As a result, semiconductor companies are increasingly turning to serial I/O architectures to achieve needed system performance. For example, high-performance ICs that are sold into wide markets, such as FPGAs and NPUs, are using serial I/Os to ensure they can match the performance of, and compete with ASICs. Using serial I/O, IC developers also are able to reduce pin count (the wired electrical I/Os that connect an IC to the NIC) on the IC. With reducing geometries, the size of most high-performance ICs is dictated by the number of pins required, rather than the amount of logic and memory embedded in the chip. As a result, using serial I/O facilitates cost reduction and reduced system power consumption, while improving the performance of both the IC itself and the overall system.

GigaChip Interface Protocol

In addition to the physical characteristics of the serial I/O, the protocol used to transmit data is also an important element that impacts speed and performance. To address this and complement our Bandwidth Engine devices, we have developed the GigaChip Interface, or GCI, which is a transport protocol optimized for efficient chip-to-chip communications. GCI is an open interface protocol, compatible with the current industry standard (Common Electrical Interface, release #11 or CEI-11). GCI can enable highly efficient serial chip-to-chip communications, and its transport efficiency averages

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90% for the data transfers it handles. GCI is included in our Bandwidth Engine ICs, and we are offering it to customers and prospective partners on terms intended to encourage widespread adoption.

High-Performance and High-Density Memory Architecture

The Bandwidth Engine uses our proprietary 1T-SRAM high density memory technology to provide the density of DRAM and the speed of SRAM. The internal multi-bank memory array architecture used in our Bandwidth Engine ICs enables concurrent access operations. We believe that this architecture is also optimized for small algorithmic operations and data transfers, such as packet header analysis.

Carrier and Enterprise Grade Quality and Reliability

Networking equipment providers focused on the carrier and enterprise market have rigid performance and reliability standards that they require their IC vendors to achieve. Our Bandwidth Engine architecture and interface is designed for data robustness and uses end-to-end error checking and correction codes. Although the Bandwidth Engine functions as more than a discrete memory device, the onboard memory array represents a significant portion of the total chip area. Memory-dominated devices require substantially different and more robust testing than non-memory ICs in order to achieve the quality and reliability requirements of advanced networking systems. We have considered these requirements for our target customers and market segments and have incorporated appropriate design and manufacturing performance margins into our Bandwidth Engine IC products.

Our Technology

Our historical business was focused on the licensing of our proprietary 1T-SRAM and SerDes I/O technologies. We have leveraged our proprietary IP to design our Bandwidth Engine IC. The following discussion explains these technologies in further detail, as well as our historical licensing activities, which we expect to continue to generate the majority of our revenues in 2012.

1T-SRAM

Our innovative 1T-SRAM technologies provide major advantages over a traditional SRAM in cell stability, memory density and power consumption, making it more economical for designers to incorporate large amounts of embedded memory in their designs. In addition, our 1T-SRAM technologies offer all the benefits of the traditional SRAM, such as low latency, high-speed and the opportunity to use a simple interface. Our 1T-SRAM technologies can achieve these advantages while utilizing standard logic manufacturing processes and providing the simple, standard SRAM interface that designers are accustomed to.

High Density

The high density of our 1T-SRAM technologies stems from the use of a single-transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM, i.e., 6T-SRAM. Increased density enables manufacturers of electronic products, such as cellular phones, video game consoles and digital cameras and camcorders, to incorporate additional functionality into a single IC, generally an SoC, resulting in overall cost savings.

Low-power Consumption

Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generate less heat than traditional SRAM when operating at the same speed. This reduces system level heat dissipation and enables reliable operation using lower cost packaging.

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High-speed

Embedded memory utilizing our 1T-SRAM technologies typically provides speeds essentially equal to or greater than the speeds of traditional SRAM and DRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than embedded 6T-SRAM technology.

SerDes (I/Os)

High-speed

To meet increasing system performance requirements, which in many cases are being driven by the growth in the Internet and the need to transmit data faster, systems are requiring both more memory and faster communication between ICs in a system. Our interface technology includes high-speed serial I/Os, called SerDes. Our SerDes technology allows for fast exchange of data between ICs in the system and can support data rates of 2.5 to 11 Gbps in a number of protocols, including XAUI, 10G KR, and PCI Express (generations 1 to 3). We are developing next generation SerDes solutions, which we are targeting to achieve data rates of 15 Gbps and support advanced geometry nodes, such as 28 nanometers, primarily for use in our IC products.

Interoperability

We make our I/O technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering their development and validation costs. Interoperability reduces development time, thereby reducing the overall time to market of our licensees' ICs.

Low power

While SerDes I/Os provide significantly enhanced performance over parallel I/Os, SerDes I/Os have higher power consumption, which is a challenge for IC designers. Our customers' SerDes I/O designs have stringent power consumption requirements, which represent a significant challenge for our engineering team. If the power consumption of the SerDes I/O is too high, the SoC must be redesigned as the power consumption budget for the SoC will be exceeded.

Our Strategy

Our primary business objective is to become an IP-rich fabless semiconductor company offering serial chip-to-chip communication solutions that deliver unparalleled bandwidth performance for next generation networking systems. The key components of the expansion of our strategic plan to become an IC supplier include the following IC-focused strategies:

Target Large and Growing Markets

Our initial strategy is to target the networking equipment market, which is a multi-billion dollar market led by companies such as Cisco Systems, Inc., Juniper Networks, Inc., Huawei Technologies, ZTE Corporation, Alcatel-Lucent and several others. To date, we have secured two low-volume design wins, which means the customer has completed its prototype evaluation and has informed us that its next generation systems will use our Bandwidth Engine IC. We are engaged with multiple customers, where we are working to achieve design wins.

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Leverage Technologies to Create New Products

Our strategy is to combine our proprietary IP and design expertise to address the needs of several upcoming generations of advanced networking equipment. We believe an IC combining our 1T-SRAM and serial I/O with logic, such as in an ALU, and other functions can provide a system-level solution and significantly improve overall system performance at lower cost and using less power. We intend to develop a Bandwidth Engine product portfolio that can serve a wide range of system performance requirements and provide cost reduction options. In addition, we can provide customized IC solutions to customers using their proprietary technology and architecture, which would allow for improved communication between our Bandwidth Engine IC and the customer's packet processor.

Another strategy is to leverage our high-speed serial I/O to create non-memory denominated ICs, which will work along side the Bandwidth Engine ICs on 100 Gbps and higher system solutions. This will provide our customers with a more complete solution, and possibly allow us to sell a chipset containing multiple MoSys ICs.

Build Long-Term Relationships with Suppliers of Packet Processors

A key consideration of network system designers is to demonstrate interoperability between our Bandwidth Engine IC and the packet processors utilized in their systems. To obtain design wins for our Bandwidth Engine IC, we must demonstrate this interoperability, and also show that our IC works optimally with the packet processor to achieve the performance requirements. To that end, we have been working closely with FPGA, ASIC and NPU providers, to demonstrate interoperability between our Bandwidth Engine IC products and their high-performance products. To facilitate the acceptance of our Bandwidth Engine ICs, we have made available development and characterization kits for system designers to evaluate and develop code for next-generation networking systems. Our characterization kits are fully-functional hardware platforms that allow FPGA and ASIC providers, and their customers, to demonstrate interoperability of the Bandwidth Engine IC with the ASIC or FPGA the designers use within their networking systems. As we engage with application-specific standard product and NPU providers, we will be developing characterization kits to support their products as well. We believe that having long-term relationships with packet processor providers is critical to our success, as such relationships may enable us to speed our time-to-market, provide us with a competitive advantage and expand our target markets.

Expand Adoption of the GigaChip Interface Protocol

Our goal is for GCI to become an open industry standard that is designed into other ICs in the system, as we believe this will further enable serial communication at the board level and encourage adoption of our Bandwidth Engine IC products. To this end, in July 2010, we launched the GigaChip Alliance, which we have been promoting to become a consortium of leading semiconductor and system companies collaborating with us to develop the industry-wide open interoperability standards and tools required to accelerate this advanced serial chip-to-chip interface. Currently, this consortium is comprised of an informal group of early adopters who have agreed to support the GCI by demonstrating interoperability of the Bandwidth Engine IC in their systems. Since 2010, we have publicly announced the following GCI supporters: Altera Corporation, Avago Technologies, Inc., LSI, Inc., NetLogic Microsystems, Inc. (recently acquired by Broadcom Corporation) and Xilinx, Inc. In addition, multiple network equipment companies, which are prospective customers, have adopted GCI.

Licensing and Distribution Strategy for our IP

Historically, we have offered our memory and I/O technologies on a worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies through product development, technology licensing and joint marketing

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relationships. We licensed our IP technology to semiconductor companies who incorporated our technology into ICs that they sold to their customers. As a result of the change in our corporate strategy, our IP licensing activities will be limited in 2012 and beyond. We intend to avoid future licensing projects that require significant use of our engineering resources, as the vast majority of our engineering personnel now work on the Bandwidth Engine ICs. However, during 2012, substantially all of our revenues will be generated from licensing and royalties related to our existing licensing arrangements, as we continue to perform and deliver under outstanding license agreements and collect royalties from 1T-SRAM licensees.

Customers in the United States accounted for 39%, 38% and 24% of our revenues in 2011, 2010 and 2009, respectively. Customers in Japan accounted for 33%, 43% and 64% of our revenues in 2011, 2010 and 2009, respectively. Customers in Taiwan accounted for 23%, 18% and 11% of our revenues in 2011, 2010 and 2009, respectively. Our remaining revenues were from customers in the rest of Asia and in Europe.

Project Licenses

Historically, we formed product development and IP licensing relationships directly with semiconductor companies. In these relationships, the prospective licensee's implementation of our technologies typically included customized development. Usually, these relationships involved both engineering work to implement our technology in the specified product and licensing the technology for manufacture and sale of the product. Although the precise terms contained in our license agreements vary, they generally include licensing fees, development fees for customizations based on the achievement of specified development milestones and royalties. The vast majority of our contracts allow for milestone billings based on work performed. If we perform the contracted services, usually the licensee is obligated to pay the license fees even if the licensee cancels the project prior to completion. The agreements often also provide for the payment of additional contract fees if we provide engineering or manufacturing support services related to the manufacture of the product. Provisions in our memory license agreements generally require the payment of royalties to us based on the future sale or manufacture of products utilizing our technologies. Generally, our project licenses grant rights on a non-exclusive, non-transferable basis, limited to the use of our technology as modified for the project covered by the license agreement. Our license agreements generally have a fixed term and are subject to renewal. Each new project requires a separate agreement or an addendum to modify an existing agreement. We are not expecting to enter into similar kinds of projects in the future, as such licenses generally require significant engineering effort and support.

Technology Licenses

We also offer our technology to semiconductor companies and foundries through 1T-SRAM and I/O technology license agreements, under which we grant the licensee the additional right to create and modify designs to offer to its own customers or use internally. The contract fees associated with these arrangements typically require the licensee to pay us to port our technology to the licensee's manufacturing process and develop a template design that the licensee will be able to use to generate future designs. These agreements also may obligate the licensee to pay contract fees upon the achievement of specified development milestones and may provide for the payment of additional contract fees for engineering or manufacturing support services. Our memory technology license agreements include royalty provisions based on the sale or manufacture of products utilizing our technologies. The technology licenses are non-transferable and authorize the licensee to modify designs for its customers or internal use from the template design that we provide under the agreement. Typically, the template design applies only to a specified manufacturing process generation or specific application. The licensee may add future process generations or uses to the license agreement for additional contract fees.

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Research and Development

Our ability to compete in the future depends on improving our technology to meet the market's increasing demand for higher performance and lower cost requirements. We have assembled a team of highly skilled engineers whose activities are focused on developing even higher density, higher bandwidth, higher speed and lower cost next generation IC products. Development of our Bandwidth Engine IC products requires the hiring of specialized chip design and product engineers, as well as significant fabrication and testing costs, including mask costs, as we bring these products to market. Our significant future research and development activities will include:

•designing next generation ICs with larger memory blocks and higher-speed SerDes;

•developing versions of our initial Bandwidth Engine IC with alternative features, such as lower-speed SerDes or smaller memory blocks to allow us to serve a broader range of applications and systems;

•porting our 1T-SRAM and SerDes technology to more advanced foundry process nodes; and

•developing new products that can leverage our proprietary IP portfolio and expand our market opportunity.

No development efforts are being dedicated to creating new or enhanced technology solely for use in licensing offerings.

As of December 31, 2011, we employed 120 individuals in engineering and research and development, of which 43 were employed in our facility in Hyderabad, India. For the years ended December 31, 2011, 2010 and 2009, research and development expenditures totaled approximately $26.2 million, $25.5 million and $19.3 million, respectively.

Sales and Marketing

As of December 31, 2011, we had 11 sales, marketing and application engineering personnel managing and supporting our IP licensing activities and securing design wins for our Bandwidth Engine product. Our application engineers actively engage with customers to introduce them to our Bandwidth Engine product capabilities and demonstrate its inter-operability within their systems. Our sales and marketing personnel are located in the United States, Japan and China. In addition to our direct sales team, we sell our technologies through sales representatives and distributors in the United States and Asia.

Our IP revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue. For the year ended December 31, 2011, Taiwan Semiconductor Manufacturing Co., Ltd., or TSMC, Renesas Electronics Corporation, or Renesas, and Broadcom represented 23%, 17% and 12% of total revenue, respectively. For the year ended December 31, 2010, Renesas, TSMC and Rohm Co., Ltd. represented 23%, 18% and 15% of total revenue, respectively. For the year ended December 31, 2009, Renesas, TSMC and Fujitsu Microelectronics, Ltd. represented 44%, 10% and 10% of total revenue, respectively.

Intellectual Property

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success, and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights.

As of December 31, 2011, we held approximately 70 U.S. and 40 foreign patents on various aspects of our technology, with expiration dates ranging from 2012 to 2028. We currently have approximately 40 pending patent applications in the U.S. and abroad. There can be no assurance that others will not

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independently develop similar or competing technology or design around any patents that may be issued to us, or that we will be able to enforce our patents against infringement.

In December 2011, we sold 43 U. S. and 30 related foreign memory technology patents for $35 million in cash pursuant to a patent purchase agreement. Under the agreement, we retained a license to all of the sold patents that is unlimited with respect to our development, manufacturing and distribution of our Bandwidth Engine IC product line and any other proprietary products that we develop as long as they are not DRAM ICs. We also retained the rights necessary to renew existing 1T-SRAM licenses and to grant licenses similar in scope to identified foundries. We also retained rights to grant licenses for our second source purposes, to enable certain kinds of technology development and to a limited extent, for certain ASIC products that incorporate one of our technology macros. However, the patent purchase agreement limits our rights to grant licenses under the sold patents outside the scope of our retained license and, in particular, limits the number of future licenses of 1T-SRAM memory technology that we can grant to developers of SoCs, which, at one time, was a principal focus of our historical 1T-SRAM licensing activities.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights are subject to a number of factors, particularly those described in Part I, Item 1A, "Risk Factors."

Competition

The markets for our Bandwidth Engine IC products are highly competitive. We believe that the principal competitive factors are:

•processing speed and performance;

•density and cost;

•low-power consumption;

•reliability;

•interface requirements;

•ease with which technology can be customized for and incorporated into customers' products; and

•level of technical support provided.

We believe that we compete favorably with respect to each of these criteria. Using our proprietary 1T-SRAM embedded memory and high-speed serial I/O IP provides our Bandwidth Engine ICs with a competitive advantage over alternative devices. Alternative solutions are either DRAM or SRAM-based and can support either the memory or speed requirements of high-performance networking systems, but generally not both. DRAM solutions provide a significant amount of memory at competitive cost, but DRAM solutions do not have the required fast access and cycle times to enable high-performance. The DRAM solutions currently used in networking systems include RLDRAM from Micron Technology, Inc. and Integrated Silicon Solutions, Inc., LLDRAM from Renesas and DDR from Elpida Memory, Inc., Micron Technology and others. SRAM solutions can meet high-speed performance requirements, but the memory size is often inadequate. The SRAM solutions currently used in networking systems primarily include QDR or similar SRAM products from Cypress Semiconductor Corporation, GSI Technology, Inc. and Samsung Electronics Co., Ltd. The majority of the currently available SRAM and DRAM solutions use a parallel rather than a serial I/O. To offset these drawbacks, system designers use more discrete memory ICs, resulting in higher power consumption and

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greater utilization of space on the line card. Our competitors include established semiconductor companies with significantly longer operating histories, greater name recognition and reputation, large customer bases, dedicated manufacturing facilities and greater financial, technical, sales and marketing resources. This may allow them to respond more quickly than we are able to respond to new or emerging technologies or changes in customer requirements. Many of our competitors also have significant influence in the semiconductor industry. They may be able to introduce new technologies or devote greater resources to the development, marketing and sales of their products than we can. Furthermore, in the event of a manufacturing capacity shortage, these competitors may be able to manufacture products when we are unable to do so.

Our Bandwidth Engine ICs compete with embedded memory solutions, stand-alone memory ICs, including both DRAM and SRAM ICs, and ASICs designed by customers in-house to meet their system requirements. Our prospective customers may be unwilling to adopt and design-in our ICs due to the uncertainties and risks surrounding designing a new IC into their systems and relying on a supplier that has almost no history of manufacturing such ICs. In addition, Bandwidth Engine ICs require the customer and its other IC suppliers to implement our new chip-to-chip communication protocol, GCI. These parties may be unwilling to do this if they believe it could adversely impact their own future product developments or competitive advantages, or if they believe it might complicate their development process or increase their cost. In order to remain competitive, we believe we must provide unparalleled memory IC solutions with the highest bandwidth capability for our target markets, which solutions are engineered and built for high-reliability carrier class and enterprise applications.

Manufacturing

We depend on third-party vendors to manufacture, package, assemble and production test our Bandwidth Engine IC products, as we do not own or operate a semiconductor fabrication, packaging or production testing facility for boards and system assembly. By outsourcing manufacturing, we are able to avoid the high cost associated with owning and operating our own facilities, allowing us to focus our efforts on the design and marketing of our products.

Manufacturing and Testing. We use TSMC to manufacture and ASE, Inc. and Evans Analytical Group, LLC, to assemble, package and production test our IC products. We utilize eSilicon Corporation to manage and support our manufacturing and testing operations.

Quality Assurance. We maintain an ongoing review of product manufacturing and testing processes. Our IC products are subjected to extensive testing to assess whether their performance exceeds the design specifications. Our test vendors provide us with immediate test data and the ability to generate characterization reports that are made available to our customers.

Employees

As of December 31, 2011, we had 143 employees, consisting of 120 in research and development and engineering, 11 in sales, marketing and application engineering and 12 in finance and administration. By location, we had 97 employees in the United States, 43 in our development center in India and 3 sales and marketing employees in Asia. We believe our future success depends, in part, on our ability to continue to attract and retain qualified technical and management personnel, particularly highly skilled design engineers involved in new product development, for which competition is intense. We believe that our employee relations are good.

Available Information

We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on

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Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934 as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read and copy any materials we file with the SEC, at the SEC's Public Reference Room at 450 Fifth Street, NW, Washington, DC 20549. You can obtain additional information about the operation of the Public Reference Room by calling the SEC at 1.800.SEC.0330. In addition, the SEC maintains a website (www.sec.gov) that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Executive Officers

The names of our executive officers and certain information about them are set forth below:

Leonard Perham 68 President and Chief Executive Officer James W. Sullivan 43 Vice President of Finance and Chief Financial Officer Thomas Riordan 55 Chief Operating Officer and Executive Vice President David DeMaria 50 Vice President of Business Operations

Leonard Perham, Mr. Perham was appointed President and Chief Executive Officer in November 2007. Mr. Perham was one of the original investors of MoSys and served on our Board of Directors from 1991 to 1997. Since 2000, Mr. Perham retired from Integrated Device Technology, Inc., or IDT, where he served as its Chief Executive Officer from 1991 and President and board member from 1986. From March 2000 to February 2012, Mr. Perham served as a member of or chairman of the board of directors of NetLogic Microsystems, a fabless semiconductor company. Mr. Perham also has been a venture partner with AsiaTech Management, a venture capital firm. Prior to joining IDT, Mr. Perham was President and CEO of Optical Information Systems, Inc., a division of Exxon Enterprises. He was also a member of the founding team at Zilog, Inc. and held management positions at Advanced Micro Devices and Western Digital. Mr. Perham received a Bachelor of Science degree in Electrical Engineering from Northeastern University.

James W. Sullivan, Mr. Sullivan became our Vice President of Finance and Chief Financial Officer in January 2008. From July 2006 until January 2008, Mr. Sullivan served as Vice President of Finance and Chief Financial Officer at Apptera, Inc., a venture-backed company providing software for mobile advertising, search and commerce. From July 2002 until June 2006, Mr. Sullivan was the Chief Financial Officer at 8x8, Inc., a provider of voice over internet protocol communication services. Mr. Sullivan's prior experience includes various positions at 8x8, Inc. and PricewaterhouseCoopers LLP. He received a Bachelor of Science degree in Accounting from New York University and is a Certified Public Accountant.

Thomas Riordan, Mr. Riordan became our Chief Operating Officer and Executive Vice President in May 2011. Prior to joining the Company, Mr. Riordan was President and Chief Executive Officer of Exclara, a fabless semiconductor supplier of ICs for solid-state lighting from 2006 until 2010. From 2000 to 2004, Mr. Riordan served as Vice President of PMC-Sierra's microprocessor division. Mr. Riordan joined PMC-Sierra in August 2000 when it purchased Quantum Effects Devices, which he had co-founded and served as President and Chief Executive Officer. Mr. Riordan serves on the board of directors of Mellanox Technologies and PLX Technology. Mr. Riordan holds Bachelor of Science and Master of Science degrees in Electrical Engineering as well as a Bachelor of Arts degree in Government from the University of Central Florida and has done post-graduate work in Electrical Engineering at Stanford University.

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David DeMaria, Mr. DeMaria became our Vice President of Business Operations in August 2008. From November 2007 until August 2008, Mr. DeMaria served as Senior Vice President at Apache Design Solutions, an electronic design automation software company. From January 2006 until November 2007, Mr. DeMaria was Chief Executive Officer of Optimal Corporation, an electronic design automation software company that he helped grow and ultimately merge with Apache Design Solutions. From October 1999 to March 2004, Mr. DeMaria served in various positions, including Executive Vice President of the systems business unit and Senior Vice President of worldwide marketing and strategy, at Cadence Design Systems. Mr. DeMaria attended Boston University for a Bachelor of Science degree in Computer Engineering.

Company Overview

MoSys, Inc. together with its subsidiaries ("MoSys", the "Company," "we" or "us") designs, develops, markets and licenses embedded memory intellectual property, or IP, used by the semiconductor industry and electronic product manufacturers. We have developed a patented semiconductor memory technology, called 1T-SRAM, which offers a combination of high density, low power consumption and high-speed at performance and cost levels that other available memory technologies do not match. We license this technology to companies that incorporate, or embed, memory on complex integrated circuits, or ICs, such as system-on-chips, or SoCs.

We also design, develop, market and license high-speed parallel and serial interface, or I/O, IP used by the semiconductor industry and electronic product manufacturers. Interface IP includes physical layer, or PHY, circuitry that allows ICs to communicate with each other or to discrete memory devices in networking, storage, computer and consumer devices. We support serial I/O technologies such as 10G KR, XAUI, PCI Express and SATA, as well as parallel interfaces like DDR3.

We generate revenue from the licensing of our memory and I/O technology, and our customers pay us fees for licensing, non-recurring engineering services, royalties, and maintenance and support. Royalty revenues are typically earned under our license agreements when our licensees manufacture or sell products that incorporate any of our memory technologies. Generally, we expect our total sales cycle, or the period from our initial discussion with a prospective licensee to our receipt of royalties from the licensee's use of our technologies, to run from 18 to 24 months. Historically, the portion of our sales cycle from the initial discussion to the receipt of license fees may run from 6 to 12 months, depending on the complexity of the proposed project and degree of development services required.

In February 2010, we announced a new product initiative to develop a family of integrated circuits products under the "Bandwidth Engine" product name. Our Bandwidth Engine family of ICs combines our 1T-SRAM high-density embedded memory with our high-speed 10 Gigabits per second (Gbps) serial I/O technology and is initially being marketed to networking systems companies and designers of advanced SoC designs. Bandwidth Engine ICs have been designed to increase system performance by using a serial I/O to increase the accesses per second between the processor and memory component in networking systems. During 2010, we invested a significant amount of our financial and engineering

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resources towards the development of our Bandwidth Engine IC, and we expect to continue to do so in 2011. We began shipping samples of our first Bandwidth Engine IC to prospective customers in December 2010. We do not expect to generate significant revenue from our Bandwidth Engine ICs until 2012 or later.

Industry Background

The personal computer, wireless communications, networking equipment and consumer electronics markets are characterized by intensifying competition, rapid innovation, increasing performance requirements and continuing cost pressures. To manufacture electronic products that achieve optimal performance and cost levels, semiconductor companies must produce integrated circuits that offer higher performance, greater functionality and lower cost.

Two important measures of performance are speed and power consumption. Higher speed ICs allow electronic products to operate faster, enabling the performance of more functions. Reducing the power consumption of integrated circuits contributes to increased battery life and reduced heat and electro-magnetic field generation in electronic products. Reduced power consumption also enables IC designers to overcome costly design hurdles, such as meeting the thermal limitations of low-cost packaging materials.

In addition to offering high-performance products, semiconductor companies must produce ICs that are cost effective. High-density ICs require less silicon, thus reducing their size and cost. Cost reductions also can be achieved by simplifying the IC's manufacturing process and improving the manufacturing yield.

To avoid the high cost of substantial redesign, semiconductor companies typically use technology that is scalable, which means it can be readily incorporated into multiple generations of manufacturing process technologies. Process technology generations are distinguished in terms of the dimension of the IC's smallest topographical features, as measured in nanometers (one billionth of a meter) (nm). The semiconductor industry has continuously developed advanced process technologies that enable the reduction of silicon area on ICs and consequently lower costs.

Importance of Integration

For decades, the semiconductor industry has continuously increased the value of ICs by improving their density, power consumption, speed and cost. The main driver for these improvements has been the success of shrinking the size of the basic semiconductor building block, or transistor. Transistors have become small enough to make it economical to combine multiple functions, such as microprocessors, graphics, memory, analog components and digital signal processors, on a single piece of silicon, resulting in a SoC. The size of devices, such as cell phones, computers and other electronic devices, continues to get smaller, resulting in the need for smaller SoCs. Highly complex ICs, such as SoCs, often offer advantages in density, power consumption, speed and cost that cannot be matched using separate, discrete ICs. SoCs are essential for most electronic products, such as cellular phones, video game consoles, portable media players, communication and networking equipment and internet appliances, to achieve increasing performance requirements at a reasonable cost.

Many large volume IC market opportunities, semiconductor companies and integrated device manufacturers, or IDMs, are developing and using a single complex SoC to replace two or three ICs. Development costs for these complex SoCs continue to escalate at a rapid rate due to the use of lower process technology solutions (e.g., 40nm and below) resulting in greater demand for licensed semiconductor intellectual property. Semiconductor companies and IDMs prefer to purchase verified IP from either an IP vendor, such as us, or a foundry that manufactures their ICs. Foundries may have their own internally developed IP or may license the IP from an IP vendor, such as us.

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Importance of Embedded Memory

Historically, semiconductor companies implemented memory by using stand-alone ICs. Rather than using stand-alone memory chips, many semiconductor companies today are embedding memory on SoCs in order to optimize performance and power consumption by eliminating the overhead and bottleneck of physical interfaces between separate, discrete devices. At the same time, the increasing sophistication of electronic products is driving a rapid increase in the amount of memory required. The amount of embedded memory area on an SoC continues to grow due to the increasing complexity of embedded applications and the rich multimedia capabilities they support requiring more data and program code storage with corresponding system price and size constraints. These constraints dictate that more information is processed in local memories on the chip rather than in discrete external memory devices.

The high cost of incorporating the memory component represents a major challenge to achieving high levels of integration. As embedded memories account for an increasing percentage of the size of highly complex ICs, they are often the slowest or limiting function in the circuit. ICs must not only contain a larger amount of embedded memory, but this memory must also be dense enough to be economically attractive and must offer sufficiently high-speed and low power consumption. In many applications, embedded memory has become a crucial design consideration for determining the overall cost and performance of highly ICs and the growing number of electronic products in which they are incorporated. In addition, embedded memory density requirements are continually increasing.

The most common form of embedded memory today is implemented using traditional static random access memory, which we refer to as traditional SRAM. This technology is in the public domain and can be designed by any semiconductor company. As memory requirements increase, however, traditional SRAM becomes more expensive compared to the total cost of the integrated circuit because it requires a substantial amount of silicon area due to its low density and consumes a significant amount of power when operating at high speeds.

To overcome the density limitations of traditional SRAM, some SoC manufacturers have utilized embedded dynamic random access memory, or embedded DRAM. While embedded DRAM has its limitations, such as being slower than traditional SRAM due to its density, requiring additional process steps that can result in lower yields and being more difficult to incorporate on ICs due to its more complex interface requirements, our challenge is to find an embedded memory solution that combines high-density, low-power consumption, high-speed and low cost.

Importance of Interface Technology

Along with embedded memory, high-speed I/Os are critical building blocks in any modern-day, high-performance SoC. High speed, efficient I/Os are needed in nearly every application as the key interface to allow the SoC to communicate with all the other ICs in the system. Historically, ICs communicated with each other through parallel I/Os, such as double data rate interfaces, including DDR2 and DDR3. As system performance requirements have increased with multiple-core processors often being used in a system, the interface requirements for communication between ICs in the systems have increased significantly. In many cases, traditional parallel I/Os are no longer optimal and become a bottleneck, limiting system performance as they can no longer keep up with the data transfer requirements the system needs at peak performance times. In effect, the parallel I/O becomes a crowded highway at rush hour where traffic can be stop-and-go and the speeds can run at less than 50% of the optimal speed.

Serial I/O technology has been used for a number of years in the communications industry, primarily on application-specific integrated circuits, or ASICs, to enable higher data transfer rates. ASICs are custom ICs developed specifically for a system manufacturer and the specific requirements of its product, and because of their custom nature, are expensive to produce. As IC geometries have

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continued to shrink, the silicon processing power has continued to increase at a fast rate with the I/O technology lagging behind. We believe the current system requirements are necessitating that the industry move to serial I/Os to meet the performance and cost requirements of system manufacturers. As a result, semiconductor companies are increasingly incorporating serial I/O capability into their ICs. For example, standard ICs and SoCs that are sold into wide markets, such as field programmable gate arrays, or FPGAs, and network processors are using serial I/Os to ensure they can match the performance of, and compete with ASICS. Using serial I/O, chip developers are also able to reduce pin counts (the wired electrical I/Os that connect the SoC to the board in the system) on the SoC. With reducing geometries, the size of most SoCs is dictated by the number of pins required rather than the amount of logic and memory embedded inside. As a result, the reduction of the number of pins that comes with the use of serial I/O facilitates cost reduction and reduced system power consumption, while improving both SoC and system performance. The different types of serial I/Os are designed to comply with industry-standard protocols, such as PCI Express, XAUI, USB and 10G KR. The protocol used is generally based on the type of system. For example, PCI Express is primarily used in computers and related computing systems, XAUI and 10G KR are primarily used in networking applications, and SATA is used in storage systems.

A challenge to developing serial I/O technology is putting together a team of skilled analog and mixed-signal designers with the requisite experience. Many large fabless semiconductor companies maintain limited serial I/O technology expertise and prefer to outsource the design and license the technology rather than incurring the cost of maintaining full capability in-house.

Our Solutions

1T-SRAM

Our innovative 1T-SRAM technologies provide major advantages over traditional SRAM in density, power consumption and cost, making it more economical for designers to incorporate large amounts of embedded memory in their designs. In addition, our 1T-SRAM technologies offer all the benefits of traditional SRAM, such as high-speed, simple interface and ease of manufacturability. Our 1T-SRAM technologies can achieve these advantages while utilizing standard logic manufacturing processes and providing the simple, standard SRAM interface that designers are accustomed to.

High Density

The high density of our 1T-SRAM technologies stems from the use of a single-transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM, i.e., 6T-SRAM. Increased density enables manufacturers of electronic products, such as cellular phones, video game consoles and digital cameras and camcorders, to incorporate additional functionality into a single integrated circuit, resulting in overall cost savings.

Low Power Consumption

Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generates less heat than traditional SRAM when operating at the same speed. This reduces system level heat dissipation costs and enables reliable operation using lower cost packaging.

High-speed

Embedded memory utilizing our 1T-SRAM technologies typically provides speeds equal to or greater than the speeds of traditional SRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than embedded 6T-SRAM technology.

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Demonstrate Manufacturing Process Independence

We have been able to implement our technology with minimal changes to the standard logic process flow. 1T-SRAM's portability, or the ease with which it can be implemented in different semiconductor manufacturing facilities, has been proven operational in the fabrication of chips at the world's largest independent foundries, including Silterra Ltd., Taiwan Semiconductor Manufacturing Co., Ltd., or TSMC, United Microelectronics Corporation, or UMC, Globalfoundries, Inc., and Semiconductor Manufacturing International Corporation, or SMIC. It has also been proven in the manufacturing processes of IDMs, such as Fujitsu Microelectronics Limited, or Fujitsu, and Renesas Electronics Corporation, or Renesas. 1T- SRAM's scalability, or the ease with which it can be implemented in different generations of manufacturing processes, has already been demonstrated in the fabrication of chips in 0.25 micron, 0.18 micron, 0.15 micron, 0.13 micron, 90nm, and 65nm process generations, with smaller geometries under development. We expect our technology to continue to scale to future process generations. This portability and scalability provides for wide availability, inexpensive implementation and quick product time to market for our licensees and has demonstrated our success with the large foundries.

Parallel and Serial I/Os

High-speed

To meet increasing system performance requirements, which in many cases are being driven by the growth in the Internet and the need to transmit data faster, systems are requiring both more memory and faster communication between the SoCs and ICs in the system. Due to our acquisition of Prism Circuits in mid-2009, our offerings also include high-speed serial I/Os, called SerDes, and parallel double data rate, or DDR, interface technology. The parallel and serial I/O technology allows for fast exchange of data between ICs in the system. Our lower-speed parallel interface technology is DDR3 and can support speeds of 1 to 3 Gbps in ICs in networking, storage, computing and other applications. Our SerDes technology can support data rates of 2.5 to 11 Gbps in a number of protocols, including XAUI, 10G KR, and PCI Express (Generations 1 to 3). We are developing next generation SerDes solutions that we are targeting to achieve data rates of 16 Gbps and higher at advanced geometry nodes (e.g., 28nm).

Interoperability

We make our I/O technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering their development and validation costs. Interoperability reduces development time, thereby reducing the overall time to market of our licensees' ICs.

Demonstrate Manufacturing Process Independence

The portability of our I/O technology is being proven in the fabrication and production of our customers' ICs at TSMC, UMC and Fujitsu Ltd., one of the largest IDMs in the world focused on the networking, computing and storage industries. The scalability of our I/O technology has already been demonstrated in the fabrication of chips in 65nm and 40nm process generations, with smaller geometries under development. We expect to continue to invest in our I/O technology to enable it to continue to scale to future process generations.

Low power

While SerDes I/Os provide significantly enhanced performance over parallel I/Os, SerDes I/Os have higher power consumption, which is a challenge for SoC designers. Our customers' SerDes I/O

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designs have stringent power consumption requirements, which represent a significant challenge for our engineering team. If the power consumption of the SerDes I/O is too high, the SoC must be redesigned as the power consumption budget for the SoC will be exceeded. To meet these challenges, we expanded our SerDes design expertise in March 2010 through the acquisition of MagnaLynx, Inc., or MagnaLynx, a small provider of I/O technology whose engineering team had significant expertise in low-power SerDes I/O.

Our Strategy

Our long-term objective is to become an IP-rich fabless semiconductor company offering both IP and ICs to our customers. We believe expanding our business strategy to become a supplier of high-performance ICs will enable us to target significantly larger markets than we currently can access with our IP. The key components of the expansion of our strategic plan to become an IC supplier include:

•developing an IC product line built around our proprietary IP and design expertise to address the needs of several upcoming generations of advanced networking equipment;

•focusing on serial rather than parallel I/Os to address the limitation of current system architectures when evaluated against future system requirements; and

•providing our Bandwidth Engine ICs with a very bandwidth efficient and logically simple interface, the Gigachip Interface, to enable serial chip to chip communication at the board level.

From an IP perspective, the semiconductor market can be divided into four major categories: microprocessors, embedded memory, analog circuit design capability and high-speed I/O. Until 2009, embedded memory had been our historical IP focus, and, through our acquisition of Prism Circuits, we added high-speed I/O and analog circuit design IP and capability. All SoCs require embedded memory, analog circuitry and high-speed I/O, and we are now able to provide three of the four significant types of IP used in SoCs. Our IP strategy is to leverage our expanded technology capabilities to increase our percentage coverage of complex, not-widely available, differentiated, embedded IP used in targeted SoCs. We believe SoCs used in the high growth consumer, converged mobile, and embedded computing market segments provide significant growth opportunities for our embedded IP, as these industries generally have significant memory requirements and are used in data-intensive applications, which require high-speed chip-to-chip communications and more analog circuitry. We intend to achieve this goal by continuing to license our technology on a worldwide basis to foundries, IDMs and semiconductor companies.

The following are integral aspects of our strategy:

Target Large and Growing Markets

We target the large and growing market for SoC applications requiring large embedded memories and high-speed I/Os, which are typically in excess of one megabyte, with our 1T-SRAM and I/O IP technologies that offer chip designers improved performance for optimizing the cost and performance of the SoC.

Although our 1T-SRAM and I/O IP technologies are applicable to many markets, we presently focus on rapidly growing product segments within the consumer electronics and communications sectors, such as networking applications targeted at addressing the bandwidth requirements generated by the growth in the Internet. These sectors increasingly require embedded memory and I/O solutions with higher density, lower power consumption, higher speeds and lower cost.

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Work Closely with Semiconductor Companies and Foundries to Deliver Optimal Technology Solutions

We work closely with semiconductor companies and foundries to gain broad and detailed insight into their and their customers' current and next-generation technology requirements. This insight helps us identify trends and focus our development efforts on optimizing our technology solution, resulting in shorter product time to market and lower costs. We plan to continue to qualify and license our technology with the leading IDMs and foundries in order to provide a wide range of manufacturing choices for our customers.

Extend our Technology Offerings

Intellectual Property

Our goal is to continue to enhance our 1T-SRAM and I/O IP technologies and increase our share of the IP market. We will continue to develop our technology in order to offer even higher density, lower power consumption, higher speed and lower cost solutions for our licensees in smaller process geometries. We continue to invest in research to develop more advanced memory technologies.

Integrated Circuits

In February 2010, we unveiled the roadmap of our Bandwidth Engine IC product line, which combines our 1T-SRAM high-density embedded memory with our high-speed 10Gbps SerDes interface technology. We expect our Bandwidth Engine ICs to address the increasing demands placed on conventional memory technology used in high-bandwidth networking systems. We believe an IC combining our 1T-SRAM and serial IO with logic and other functions can provide a system-level solution and significantly improve overall system performance at lower cost and using less power. A major challenge to system designers is what we call the "memory performance barrier." Processor performance in applications such as computing and networking has continued to nearly double every 18 months, or even faster, while the performance of memory technology has generally been able to double every 10 years. Our Bandwidth Engine IC will provide up to two billion accesses per second, over twice the performance of current memory based solutions, and enable system designers to significantly narrow that gap. Customers that design Bandwidth Engine ICs into their systems will re-architect those systems at the board level and use our product to replace traditional memory solutions. When compared with existing solutions, the Bandwidth Engine is expected to:

•increase performance up to four times;

•reduce power by approximately 50%;

•reduce cost by greater than 50%; and

•result in a dramatic reduction in IC pin counts on the board.

To complement our Bandwidth Engine devices, we have also introduced the GigaChip Interface, an open interface, compatible with the current industry standard (CEI-11), which can enable highly efficient serial chip-to-chip communications. The GigaChip Interface is included in our Bandwidth Engine ICs, and we are offering it to customers and prospective partners on terms intended to encourage its widespread adoption. Our goal is for the GigaChip Interface to become an open industry standard that is designed into other ICs in the system, as we believe this will further enable serial communication at the board level and encourage adoption of Bandwidth Engine devices. To this end, in July 2010 we launched the GigaChip Alliance, which we anticipate will become a consortium of leading semiconductor and system companies collaborating with us to develop the industry-wide open interoperability standards and tools required to accelerate this advanced serial chip-to-chip interface.

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We began shipping samples of the Bandwidth Engine ICs to prospective customers and partners in December 2010. We do not expect to generate meaningful revenue from the Bandwidth Engine product line until 2012 or later. During 2011, we will be focused on—

•bringing this new IC product to market;

•completing the engineering processes necessary to demonstrate the necessary quality and reliability required by system suppliers;

•expanding use of the GigaChip Interface and increase participation in the GigaChip Alliance;

•developing an IC sales channel;

•obtaining our first customer design wins late in the year; and

•commencing development of our next generation of Bandwidth Engine ICs.

Licensing and Distribution Strategy

We offer our memory and I/O IP technology on a worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies through product development, technology licensing and joint marketing relationships.

We license our IP technology to semiconductor companies who incorporate our technology into ICs that they sell to their customers. We also sell to system companies that design ASICs. In addition, we engage in joint marketing activities with foundries, other IP companies and design companies to promote our technology to a wide base of customers. These distribution channels have broadened the acceptance and availability of our technology in the industry. As our technology becomes available through an increasing number of channels, we believe it will be less likely that customers will have to alter their procurement practices in order to acquire our technology. We intend to continue to significantly expand this base of strategic relationships to further proliferate our technology.

Customers in Japan accounted for 43%, 64% and 62% of our revenues in 2010, 2009 and 2008, respectively. Customers in the United States accounted for 38%, 24% and 13% of our revenues in 2010, 2009 and 2008, respectively. Customers in Taiwan accounted for 18%, 11% and 16% of our revenues in 2010, 2009 and 2008, respectively, while our remaining revenues were from customers in the rest of Asia and in Europe.

Project Licenses

We form product development and IP licensing relationships directly with semiconductor companies. In these relationships, the prospective licensee's implementation of our technologies typically includes customized development. Usually, these relationships involve both engineering work to implement our technology in the specified product and licensing the technology for manufacture and sale of the product. Although the precise terms contained in our license agreements vary, they generally include licensing fees, development fees for customizations based on the achievement of specified development milestones, and royalties. The vast majority of our contracts allow for milestone billings based on work performed. If we perform the contracted services, usually the licensee is obligated to pay the license fees even if the licensee cancels the project prior to completion. The agreements often also provide for the payment of additional contract fees if we provide engineering or manufacturing support services related to the manufacture of the product. Provisions in our memory license agreements generally require the payment of royalties to us based on the future sale or manufacture of products utilizing our technologies. Generally, our project licenses grant rights on a non-exclusive, non-transferable basis, limited to the use of our technology as modified for the project covered by the license agreement. Our license agreements generally have a fixed term and are subject

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to renewal. Each new project requires a separate agreement or an addendum to modify an existing agreement.

We have IP license agreements with many companies, including, but not limited to, Agilent Technologies, Analog Devices, Inc., Applied Micro Circuits Corporation, Broadcom Corporation, Dialog Semiconductor, Entropic Communications, Inc., eSilicon Corporation, Fujitsu, Himax Technologies, Ltd., Hitachi, Ltd., Kawasaki Micoroelectronics, Inc., LG Electronics, Inc., LSI Logic Corporation, Marvell Semiconductor, Inc., Matsushita Communication Industrial Co., Ltd., Mindspeed Technologies, Inc., National Semiconductor Corporation, Netlist, Inc., Nexuschips Co. Ltd., Open-Silicon, Inc., Orise Technology Co. Inc., Philips Semiconductors, Inc., Pixelworks, Inc., Pixim, Inc., Progate Group Corporation, Realtek Semiconductor Corporation, Renesas Electronics Corporation, Rohm Co. Ltd, Sanyo Electric Co., Ltd., Silterra Ltd., SMIC, Sony Corporation, Synaptics, Inc., TSMC, UMC, Via Technologies, Inc., Xilinx, Inc., and Yamaha Corporation.

Technology Licenses

We also offer our technology to semiconductor companies and foundries through 1T-SRAM and I/O technology IP license agreements, under which we grant the licensee the additional right to create and modify designs to offer to its own customers or use internally. The contract fees associated with these arrangements typically require the licensee to pay us to port our technology to its manufacturing process and develop a template design that the licensee will be able to use to generate future designs. These agreements also may obligate the licensee to pay contract fees upon the achievement of specified development milestones and may provide for the payment of additional contract fees for engineering or manufacturing support services. Our memory technology license agreements include royalty provisions based on the sale or manufacture of products utilizing our technologies. The technology licenses are non-transferable and authorize the licensee to modify designs for its customers or internal use from the template design that we provide under the agreement. Typically, the template design applies only to a specified manufacturing process generation or specific application. The licensee may add future process generations or uses to the license agreement for additional contract fees.

Research and Development

Our ability to compete in the future depends on improving our technology to meet the market's increasing demand for higher performance and lower cost requirements. We have assembled a team of highly skilled engineers whose activities are focused on developing even higher density, lower power consumption, higher speed and lower cost memory and I/O IP designs. We expect to continue to focus our research and development efforts by extending our IP technologies to smaller process geometries, porting our technology to additional foundries and semiconductor manufacturing facilities. In addition, development of our Bandwidth Engine IC products requires the hiring of specialized chip design and product engineers as well as significant fabrication and testing costs, including mask costs, as we bring these products to market.

As of December 31, 2010, we employed 135 individuals in engineering and research and development, of which 55 are employed in our facility in Hyderabad, India. For the years ended December 31, 2010, 2009 and 2008, research and development expenditures totaled approximately $25.5 million, $19.3 million and $17.2 million, respectively.

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Sales and Marketing

As of December 31, 2010, we had 13 sales, marketing and application engineering personnel managing and supporting our IP licensing activities. Our sales and marketing personnel are located in the United States and Japan. In addition to our direct sales team, we sell our technologies through a sales representative in Europe. The sales personnel manage the negotiation of license agreements, provide technical support during the sales cycle to licensees and manage delivery under the contracts. In late 2010, we hired a vice president of integrated circuit sales to begin focusing on developing a sales channel for our Bandwidth Engine product line.

Our overall revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue. For the year ended December 31, 2010, Renesas (formerly NEC Electronics), TSMC and Rohm represented 23%, 18% and 15% of total revenue, respectively. For the year ended December 31, 2009, Renesas, TSMC and Fujitsu represented 44%, 10% and 10% of total revenue, respectively. For the year ended December 31, 2008, Renesas and TSMC represented 55% and 13% of total revenue, respectively.

Intellectual Property

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success, and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights. As of December 31, 2010, we held approximately 110 U.S. and approximately 55 foreign patents on various aspects of our technology, with expiration dates ranging from 2012 to 2028. We currently have approximately 75 pending patent applications in the U.S. and abroad. There can be no assurance that others will not independently develop similar or competing technology or design around any patents that may be issued to us, or that we will be able to enforce our patents against infringement.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights are subject to a number of factors, particularly those described in Part I, Item 1A, "Risk Factors."

Competition

The markets for our memory and I/O technologies are highly competitive. We believe that the principal competitive factors are:

•density and cost;

•power consumption;

•speed;

•portability to different manufacturing processes;

•scalability to different manufacturing process generations;

•reliability and low manufacturing costs;

•interface requirements;

•the ease with which technology can be customized for and incorporated into customers' products; and

•level of technical support provided.

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In order to remain competitive, we believe we must continue to provide higher density, lower power consumption, higher speed and lower cost technology solutions. Our 1T-SRAM technologies compete primarily with traditional SRAM, which is currently the preferred choice for embedded memory solutions in SoCs requiring less density, and embedded DRAM. Companies providing traditional SRAM embedded memories include ARM Holdings PLC and Synopsys, Inc. Embedded DRAM is offered by major foundries and IC suppliers such as TSMC, Toshiba and International Business Machines Corporation (IBM), among others. Foundries offering embedded DRAM are also able to provide their customers with IC design services, include memory designs for their customers ICs. In that case, the cost of the embedded memory and design are included in the wafer cost charged by the foundry. In these cases, companies would not have to license the use of their memory design from a memory provider like us, but would get the memory design from their foundry partner. We have licensed our 1T-SRAM technology to TSMC, and, under that license, TSMC is able to offer embedded DRAM solutions directly to its customers, obviating the need for those customers to obtain a license and do business directly with us. While TSMC does pay us royalties based on wafers it produces that incorporate our technology, these royalties are lower than the license and royalty fees we have historically received from customers that came to us for a technology license and memory design.

Not all embedded memory applications benefit sufficiently from the technological advantages offered by our 1T-SRAM to justify the increased cost to the licensee. Our licensees and prospective licensees can meet their current needs for embedded memory using other memory solutions with different cost and performance parameters. For example, our technologies are not suitable for replacing lower-cost traditional DRAM memory chips if higher access speed is unnecessary. In addition, alternative solutions may be more cost-effective for memory block sizes of less than one megabit, or applications in which the embedded memory portion is less than 20% of the total chip area.

Moreover, some companies assess greater uncertainty and risk in relying on the newer generations of 1T-SRAM technologies, including the uncertainties surrounding the manufacturing process. As a result, our ability to compete effectively may be limited because such companies may prefer to use more established traditional memory solutions that are freely available without a license. In the current macroeconomic environment, we believe that, notwithstanding the competitively superior features of our technology, companies, including some of our current and past licensees, will continue to seek new ways to reduce their costs, which could include modifying designs to accommodate traditional memory solutions instead of licensing 1T-SRAM from us or our technology licensees.

Our SerDes and DDR IP solutions compete with offerings from Synopsys, Inc., Gennum Corporation, Analog Bits, Inc. and other IP and ASIC providers, as well as the internal design teams of customers. Some of these larger competitors, such as Synopsys, are able to bundle their I/O technology products with their electronic design automation software and/or IC controller solutions and provide lower pricing on the packaged offering. In addition, customers often prefer to use IP solutions that have been fabricated in silicon and considered production-ready, which our competitors may be able to provide more timely than we can. We continue to focus on expanding our portfolio of these 'off-the-shelf' or production-ready IP solutions, which require significantly less commitment of our engineering personnel and generate higher gross margins. We also have the design expertise to customize the I/O IP to precisely meet customers' design requirements, which some of our competitors are unwilling or unable to do.

As part of our I/O product offerings we also provide customers with analog circuitry designs such as phase lock loops, or PLLs, and converters, which convert analog signals to digital format and digital signals to analog format. We generally do not sell our analog circuitry designs as stand-alone IP, but rather include them with our I/O technology offerings. These analog circuitry designs are commodity offering and are available from analog technology providers, such as Analog Bits.

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We believe our interface solutions can meet the need for faster rates of data transfer, such as 10Gbps and greater, which the industry is striving for. Time to market is critical for our customers. Therefore, having IP that conforms to widely-used industry protocols or standards is an important advantage of our I/O technology to reduce the amount of design time required to produce an IC. We continue to expand the protocols that we can support to ensure that we can remain competitive.

Employees

As of December 31, 2010, we had 162 employees, consisting of 135 in research and development and engineering, 14 in sales, marketing and application engineering and 13 in finance and administration. By location, we had 105 employees in the United States, 55 in our development center in India and 2 sales and marketing employees in Asia. We believe our future success depends, in part, on our ability to continue to attract and retain qualified technical and management personnel, particularly highly skilled design engineers involved in new product development, for which competition is intense. We believe that our employee relations are good.

Available Information

We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934 as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read and copy any materials we file with the SEC, at the SEC's Public Reference Room at 450 Fifth Street, NW, Washington, DC 20549. You can obtain additional information about the operation of the Public Reference Room by calling the SEC at 1.800.SEC.0330. In addition, the SEC maintains a website (www.sec.gov) that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Executive Officers

The names of our executive officers and certain information about them are set forth below:

Leonard Perham 67 President and Chief Executive Officer James W. Sullivan 42 Vice President of Finance and Chief Financial Officer Sundari Mitra 47 Executive Vice President of Engineering David DeMaria 49 Vice President of Business Operations

Leonard Perham, Mr. Perham was appointed President and Chief Executive Officer in November 2007. Mr. Perham was one of the original investors of MoSys and served on our Board of Directors from 1991 to 1997. Until his retirement from Integrated Device Technology, Inc., or IDT, in 2000, Mr. Perham served as its Chief Executive Officer from 1991 and President and board member from 1986. Mr. Perham has served as chairman of the board of directors of NetLogic Microsystems, a fabless semiconductor company, and has been a venture partner with AsiaTech Management, a venture capital firm. Prior to joining IDT, Mr. Perham was President and CEO of Optical Information Systems, Inc., a division of Exxon Enterprises. He was also a member of the founding team at Zilog Inc. and held management positions at Advanced Micro Devices and Western Digital. Mr. Perham received a Bachelor of Science degree in Electrical Engineering from Northeastern University.

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James W. Sullivan, Mr. Sullivan became our Vice President of Finance and Chief Financial Officer in January 2008. From July 2006 until January 2008, Mr. Sullivan served as Vice President of Finance and Chief Financial Officer at Apptera, Inc., a venture-backed company providing software for mobile advertising, search and commerce. From July 2002 until June 2006, Mr. Sullivan was the Vice President of Finance and Chief Financial Officer at 8x8, Inc., a provider of voice over internet protocol communication services. Mr. Sullivan's prior experience includes various positions at 8x8, Inc. and PricewaterhouseCoopers LLP. He received a Bachelor of Science degree in Accounting from New York University and is a Certified Public Accountant.

Sundari Mitra, Ms. Mitra became our Executive Vice President of Engineering in June 2009. Prior to joining the Company, Ms. Mitra founded and served as Chief Executive Officer of Prism Circuits from its inception in February 2006 until our acquisition of Prism Circuits in June 2009. Prior to founding Prism Circuits, Ms. Mitra served as a Director of Engineering at Sun Microsystems, Inc. from June 2002 to August 2004. Ms. Mitra holds a Masters of Science degree in Electrical Engineering from the University of Illinois and a Bachelors of Science degree in Electrical Engineering from Baroda University in India.

David DeMaria, Mr. DeMaria became our Vice President of Business Operations in August 2008. From November 2007 until August 2008, Mr. DeMaria served as Senior Vice President at Apache Design Solutions, an electronic design automation software company. From January 2006 until November 2007, Mr. DeMaria was Chief Executive Officer of Optimal Corporation, an electronic design automation software company that he helped grow and ultimately merge with Apache Design Solutions. From October 1999 to March 2004, Mr. DeMaria served in various positions, including Executive Vice President of the systems business unit and Senior Vice President of worldwide marketing and strategy, at Cadence Design Systems. Mr. DeMaria attended Boston University for a Bachelor of Science degree in Computer Engineering.

Company Overview

MoSys, Inc. together with its subsidiaries ("MoSys", the "Company", "we" or "us") designs, develops, markets and licenses embedded memory intellectual property, or IP, used by the semiconductor industry and electronic product manufacturers. We have developed a patented semiconductor memory technology, called 1T-SRAM, which offers a combination of high density, low power consumption and high-speed at performance and cost levels that other available memory technologies do not match. We license this technology to companies that incorporate, or embed, memory on complex integrated circuits, or ICs, such as system-on-chips, or SoCs.

We also design, develop, market and license high-speed parallel and serial interface, or I/O, IP used by the semiconductor industry and electronic product manufacturers. Interface IP includes physical layer (PHY) circuitry that allows ICs to communicate with each other or to discrete memory devices in networking, storage, computer and consumer devices. We support serial I/O technologies such as 10G KR, XAUI, PCI Express and SATA, as well as parallel interfaces like DDR3.

We generate revenue from the licensing of our memory and I/O technology, and our customers pay us fees for licensing, non-recurring engineering services, royalties, and maintenance and support. Royalty revenues are typically earned under our license agreements when our licensees manufacture or sell products that incorporate any of our memory technologies. Generally, we expect our total sales cycle, or the period from our initial discussion with a prospective licensee to our receipt of royalties from the licensee's use of our technologies, to run from 18 to 24 months. Historically, the portion of our sales cycle from the initial discussion to the receipt of license fees may run from 6 to 12 months, depending on the complexity of the proposed project and degree of development services required.

In the third quarter of 2007, we acquired analog/mixed-signal integrated circuit designs, intellectual property, related assets and subsidiaries from Atmel Corporation, or Atmel, and LSI Design and Integration Corporation, or LDIC. In December 2008, as part of our initiative to exit unprofitable and non-core product lines, we announced our plan to cease all further work and sales activities on the acquired analog/mixed-signal products. In the first half of 2009, we closed our subsidiaries in China and Romania and eliminated approximately 90 employees.

In June 2009, we completed the acquisition of substantially all the assets and business of Prism Circuits, Inc. (Prism Circuits), a provider of high-speed parallel and serial I/O technology. Through this

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acquisition we acquired high-speed and serial I/O technology. We believe the integration of our patented memory IP and the I/O technology acquired from Prism Circuits will allow us to provide a more comprehensive and competitive solution to our customers, especially in the networking and communications markets. With the acquisition, we added 22 engineers, in Sunnyvale, California and 30 employees, mainly engineers, in Hyderabad, India. These engineers are experienced in interface technology development and analog/mixed-signal applications. We paid Prism Circuits approximately $13.6 million in cash, net of cash received in the acquisition and assumed liabilities totaling approximately $2.4 million as consideration for the acquired assets. We also agreed to pay up to an additional $6.5 million of cash as an earn-out payment, contingent upon our achievement of specified milestones relating to the acquired business during the twelve-month period following the closing date. Any earn-out payment to the extent earned will likely be paid in the third quarter of 2010. In addition, we granted options to purchase 3.6 million shares of the Company's common stock to the newly hired Prism Circuits employees.

In February 2010, we announced the commencement of a new product initiative to develop a family of IC products under the "Bandwidth Engine" product name. The Bandwidth Engine will combine our 1T-SRAM high-density embedded memory with our high-speed 10 Gigabits per second (Gbps) serial communication I/O technology and will initially be marketed to networking systems companies. The Bandwidth Engine is being designed to increase system performance by using a serial I/O to increase the accesses per second between the processor and memory component in networking systems. Based on our current development schedule, we expect to have samples of the Bandwidth Engine available for customers by the fourth quarter of 2010.

On March 25, 2010, we acquired all of the outstanding stock of MagnaLynx, Inc. (MagnaLynx), a provider of semiconductor interface technology. Under the terms of the merger agreement, at closing we paid approximately $1.3 million to the shareholders of MagnaLynx and paid approximately $2.2 million to settle debt and certain other liabilities of MagnaLynx. An additional $0.5 million is payable 18 months after the closing, net of any costs related to indemnification claims that may arise during such 18 month period. In addition, we agreed to pay up to an additional $1.0 million, net of any costs related to indemnification claims, to the former shareholders of MagnaLynx shortly after the first anniversary of the closing date, as earn-out consideration based on MagnaLynx meeting certain contractually agreed-upon development milestones.

Industry Background

The personal computer, wireless communications, networking equipment and consumer electronics markets are characterized by intensifying competition, rapid innovation, increasing performance requirements and continuing cost pressures. To manufacture electronic products that achieve optimal performance and cost levels, semiconductor companies must produce integrated circuits that offer higher performance, greater functionality and lower cost.

Two important measures of performance are speed and power consumption. Higher speed ICs allow electronic products to operate faster, enabling the performance of more functions. Reducing the power consumption of integrated circuits contributes to increased battery life and reduced heat and electro-magnetic field generation in electronic products. Reduced power consumption also enables IC designers to overcome costly design hurdles, such as meeting the thermal limitations of low-cost packaging materials.

In addition to offering high-performance products, semiconductor companies must produce ICs that are cost effective. High-density ICs require less silicon, thus reducing their size and cost. Cost reductions also can be achieved by simplifying the IC's manufacturing process and improving the manufacturing yield.

To avoid the high cost of substantial redesign, semiconductor companies typically use technology that is scalable, which means it can be readily incorporated into multiple generations of manufacturing

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process technologies. Process technology generations are distinguished in terms of the dimension of the IC's smallest topographical features, as measured in microns (one millionth of a meter) or nanometers (one billionth of a meter) (nm). The semiconductor industry has continuously developed advanced process technologies that enable the reduction of silicon area on ICs and consequently lower costs.

Importance of Integration

For decades, the semiconductor industry has continuously increased the value of ICs by improving their density, power consumption, speed and cost. The main driver for these improvements has been the success of shrinking the size of the basic semiconductor building block, or transistor. Transistors have become small enough to make it economical to combine multiple functions, such as microprocessors, graphics, memory, analog components and digital signal processors, on a single piece of silicon, resulting in a SoC. The size of devices, such as cell phones, computers and other electronic devices, continues to get smaller, resulting in the need for smaller SoCs. Highly complex ICs, such as SoCs, often offer advantages in density, power consumption, speed and cost that cannot be matched using separate, discrete ICs. SoCs are essential for most electronic products, such as cellular phones, video game consoles, portable media players, communication and networking equipment and internet appliances, to achieve increasing performance requirements at a reasonable cost.

For many large volume IC market opportunities, semiconductor companies and integrated device manufacturers, or IDMs, are developing and using a single complex SoC to replace two or three ICs. Development costs for these complex SoCs continue to escalate at a rapid rate due to the use of lower process technology solutions (e.g., 65nm and below) resulting in greater demand for licensed semiconductor intellectual property. Semiconductor companies and IDMs prefer to purchase verified IP from either an IP vendor, such as us, or a foundry that manufactures their ICs. Foundries may have their own internally developed IP or may license the IP from an IP vendor, such as us.

Importance of Embedded Memory

Historically, semiconductor companies implemented memory by using stand-alone ICs. Rather than using stand-alone memory chips, many semiconductor companies today are embedding memory on SoCs in order to optimize performance and power consumption by eliminating the overhead and bottleneck of physical interfaces between separate, discrete devices. At the same time, the increasing sophistication of electronic products is driving a rapid increase in the amount of memory required. The amount of embedded memory area on an SoC continues to grow due to the increasing complexity of embedded applications and the rich multimedia capabilities they support requiring more data and program code storage with corresponding system price and size constraints. These constraints dictate that more information is processed in local memories on the chip rather than in discrete external memory devices.

The high cost of incorporating the memory component represents a major challenge to achieving high levels of integration. As embedded memories account for an increasing percentage of the size of highly complex ICs, they are often the slowest or limiting function in the circuit. ICs must not only contain a larger amount of embedded memory, but this memory must also be dense enough to be economically attractive and must offer sufficiently high-speed and low power consumption. In many applications, embedded memory has become a crucial design consideration for determining the overall cost and performance of highly ICs and the growing number of electronic products in which they are incorporated. In addition, embedded memory density requirements are continually increasing.

The most common form of embedded memory today is implemented using traditional static random access memory, which we refer to as traditional SRAM. This technology is in the public domain and can be designed by any semiconductor company. As memory requirements increase, however, traditional SRAM becomes more expensive compared to the total cost of the integrated circuit because it requires a substantial amount of silicon area due to its low density and consumes a significant amount of power when operating at high speeds.

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To overcome the density limitations of traditional SRAM, some SoC manufacturers have utilized embedded dynamic random access memory, or embedded DRAM. While embedded DRAM has its limitations, such as being slower than traditional SRAM due to its density, requiring additional process steps that can result in lower yields and being more difficult to incorporate on ICs due to its more complex interface requirements, our challenge is to find an embedded memory solution that combines high-density, low-power consumption, high-speed and low cost.

Importance of Interface Technology

Along with embedded memory, high-speed I/Os are critical building blocks in any modern-day, high-performance SoC. High speed, efficient I/Os are needed in nearly every application as the key interface to allow the SoC to communicate with all the other ICs in the system. Historically, ICs communicated with each other through parallel I/Os, such as double data rate interfaces, including DDR 2 and DDR 3. As system performance requirements have increased with multiple-core processors often being used in a system, the interface requirements for communication between ICs in the systems have increased significantly. In many cases, traditional parallel I/Os are no longer optimal and become a bottleneck, limiting system performance as they can no longer keep up with the data transfer requirements the system needs at peak performance times. In effect, the parallel I/O becomes a crowded highway at rush hour where traffic can be stop-and-go and the speeds can run at less than 50% of the optimal speed.

Serial I/O technology has been used for a number of years in the communications industry, primarily on application-specific integrated circuits, or ASICs, to enable higher data transfer rates. ASICs are custom ICs developed specifically for a system manufacturer and the specific requirements of its product, and because of their custom nature, are expensive to produce. As IC geometries have continued to shrink, the silicon processing power has continued to increase at a fast rate with the I/O technology lagging behind. We believe the current system requirements are necessitating that the industry move to serial I/Os to meet the performance and cost requirements of system manufacturers. Using serial I/O, chip developers are also able to reduce pin counts (the wired electrical I/Os that connect the SoC to the board in the system) on the SoC. With reducing geometries, the size of most SoCs is dictated by the number of pins required rather than the amount of logic and memory embedded inside. As a result, the reduction of the number of pins that comes with the use of serial I/O facilitates cost reduction and reduced system power consumption, while improving both SoC and system performance. The different types of serial I/Os are designed to comply with industry-standard protocols, such as PCI Express, XAUI, USB and 10G KR. The protocol used is generally based on the type of system. For example, PCI Express is primarily used in computers and related computing systems, XAUI and 10G KR are primarily used in networking applications, and SATA is used in storage systems.

A challenge to developing serial I/O technology is putting together a team of skilled analog and mixed-signal designers with the requisite experience. Many large fabless IC companies maintain limited serial I/O technology expertise and prefer to outsource the design and license the technology rather than incurring the cost of maintaining full capability in-house.

Our Solutions

1T-SRAM

Our innovative 1T-SRAM technologies provide major advantages over traditional SRAM in density, power consumption and cost, making it more economical for designers to incorporate large amounts of embedded memory in their designs. In addition, our 1T-SRAM technologies offer all the benefits of traditional SRAM, such as high-speed, simple interface and ease of manufacturability. Our 1T-SRAM technologies can achieve these advantages while utilizing standard logic manufacturing processes and providing the simple, standard SRAM interface that designers are accustomed to.

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High Density

The high density of our 1T-SRAM technologies stems from the use of a single- transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM, i.e., 6T-SRAM. Increased density enables manufacturers of electronic products, such as cellular phones, video game consoles and digital cameras and camcorders, to incorporate additional functionality into a single integrated circuit, resulting in overall cost savings.

Low Power Consumption

Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generates less heat than traditional SRAM when operating at the same speed. This reduces system level heat dissipation costs and enables reliable operation using lower cost packaging.

High-speed

Embedded memory utilizing our 1T-SRAM technologies typically provides speeds equal to or greater than the speeds of traditional SRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds, significantly faster than embedded 6T-SRAM technology.

Demonstrate Manufacturing Process Independence

We have been able to implement our technology with minimal changes to the standard logic process flow. 1T-SRAM's portability, or the ease with which it can be implemented in different semiconductor manufacturing facilities, has been proven operational in the fabrication of chips at the world's largest independent foundries, including Silterra Ltd., Taiwan Semiconductor Manufacturing Co., Ltd., or TSMC, United Microelectronics Corporation, or UMC, Globalfoundries, Inc., and Semiconductor Manufacturing International Corporation, or SMIC. It has also been proven in the manufacturing processes of IDMs, such as Fujitsu Limited, or Fujitsu, and NEC Electronics, or NEC. 1T-SRAM's scalability, or the ease with which it can be implemented in different generations of manufacturing processes, has already been demonstrated in the fabrication of chips in 0.25 micron, 0.18 micron, 0.15 micron, 0.13 micron, 90nm, and 65nm process generations, with smaller geometries under development. We expect our technology to continue to scale to future process generations. This portability and scalability provides for wide availability, inexpensive implementation and quick product time to market for our licensees and has demonstrated our success with the large foundries.

Parallel and Serial I/Os

High-speed

To meet increasing system performance requirements, which in many cases is being driven by the growth in the Internet and the need to transmit data faster, systems are requiring both more memory and faster communication between the SoCs and ICs in the system. When we acquired Prism Circuits in mid-2009, their focus was on developing very high speed serial I/Os, called SerDes, which had data transmission speeds of up to10 Gbps, with higher speed I/Os under development. When Prism Circuits was formed in 2006, its initial focus was on parallel DDR interface technology and those development efforts have also continued. Today, we offer both parallel and serial I/O technology that allows for fast exchange of data between ICs in the system. Our lower-speed parallel interface technology is DDR 3 and can support speeds of 1 to 3 Gbps in ICs in networking, storage, computing and other applications. Our SerDes technology can support data rates of 2.5 to 10 Gbps in a number of protocols, including XAUI, 10G KR, and PCI Express (Generations 1 to 3). We are developing next generation SerDes solutions that we are targeting to achieve data rates of 16 Gbps and higher at advanced geometry nodes (e.g., 28 nm).

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Interoperability

We make our I/O technologies compliant with industry standards so that they can interoperate with interfaces on existing ICs. In addition, we make them programmable to support multiple data rates, which allows for greater flexibility for the system designer, while lowering their development and validation costs. Interoperability reduces development time, thereby reducing the overall time to market of our licensees' ICs.

Demonstrate Manufacturing Process Independence

The portability of our I/O technology is being proven in the fabrication of our customer's ICs at TSMC, UMC and Fujitsu, one of the largest IDMs in the world focused on the networking, computing and storage industries. The scalability of our I/O technology has already been demonstrated in the fabrication of chips in 0.65 micron and 0.40 micron process generations, with smaller geometries under development. We expect our I/O technology to continue to scale to future process generations. To date, due to the short operating history of Prism Circuits prior to the acquisition, none of our I/O customers have commenced shipping ICs, which is a key data point that our prospective customers consider in evaluating our I/O technology.

Our Strategy

The semiconductor IP market can be divided into four major categories: microprocessors, embedded memory, analog circuit design capability and high-speed I/O. Embedded memory has been our historical focus, and, through our 2009 acquisition of Prism Circuits, we have now added high-speed I/O and analog circuit design capability. Our strategy is to leverage our expanded technology capabilities to increase our percentage coverage of complex, not-widely available, differentiated, embedded IP used in targeted SoCs. We believe the high growth connected consumer, converged mobile, and embedded computing market segments provide significant growth opportunities for our embedded IP, as these industries generally have significant memory requirements and are used in data-intensive applications, which require high-speed chip-to-chip communications. We intend to achieve this goal by continuing to license our technology on a worldwide basis to foundries, IDMs and semiconductor companies.

We initiated development of our Bandwidth Engine IC product line in the second half of 2009. We believe that the combination of 1T-SRAM and high-speed SerDes, implemented in a single IC, will be a compelling solution to address the needs of networking system designers.

The following are integral aspects of our strategy:

Target Large and Growing Markets

We target the large and growing market for SoC applications requiring large embedded memories and high-speed I/Os, which are typically in excess of one megabyte, with our 1T-SRAM and I/O IP technologies that offer chip designers improved performance for optimizing the cost and performance of the SoC.

Although our 1T-SRAM and I/O IP technologies are applicable to many markets, we presently focus on rapidly growing product segments within the consumer electronics and communications sectors, such as networking applications targeted at addressing the bandwidth requirements generated by the growth in the Internet. These sectors increasingly require embedded memory and I/O solutions with higher density, lower power consumption, higher speeds and lower cost. Over the longer term we intend to identify and address other markets that are projected to achieve strong, long-term growth.

Work Closely with Semiconductor Companies and Foundries to Deliver Optimal Technology Solutions

We work closely with semiconductor companies and foundries to gain broad and detailed insight into their and their customers' current and next-generation technology requirements. This insight helps

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us identify trends and focus our development efforts on optimizing our technology solution, resulting in shorter product time to market and lower costs. We plan to continue to qualify and license our technology with the leading IDMs and foundries in order to provide a wide range of manufacturing choices for our customers.

Extend our Technology Offerings

Our goal is to continue to enhance our 1T-SRAM and I/O IP technologies and increase our share of the IP market. We will continue to develop our technology in order to offer even higher density, lower power consumption, higher speed and lower cost solutions for our licensees in smaller process geometries. We continue to invest in research to develop more advanced memory technologies, including our embedded non-volatile memory solution, 1T-Flash, which is still under development.

With the announcement of our new Bandwidth Engine IC, we expect to provide a system level solution for networking systems, which we believe will provide higher bandwidth at lower cost and power consumption. We believe that customers that design the Bandwidth Engine into their system will re-architect the system at the board level and will result in the replacement of traditional memory solutions. To complement the Bandwidth Engine, we are also introducing the GigaChip Interface, which will be an open I/O compatible with the current industry standard (CEI-11) that will enable highly efficient serial chip-to-chip communications. The GigaChip Interface will be used in the Bandwidth Engine, and we expect to offer it to customers and prospective partners on terms that will encourage its widespread adoption. Our goal is for the GigaChip Interface to become an industry standard that is designed into other ICs in the system, as we believe this will encourage adoption of the Bandwidth Engine.

Licensing and Distribution Strategy

We offer our memory and I/O technology on a worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies through product development, technology licensing and joint marketing relationships.

We license our technology to semiconductor companies who incorporate our technology into ICs that they sell to their customers. We also sell to system companies that design ASICs. In addition, we engage in joint marketing activities with foundries, other IP companies and design companies to promote our technology to a wide base of customers. These distribution channels have broadened the acceptance and availability of our technology in the industry. As our technology becomes available through an increasing number of channels, we believe it will be less likely that customers will have to alter their procurement practices in order to acquire our technology. We intend to continue to significantly expand this base of strategic relationships to further proliferate our technology.

Customers in Japan accounted for 64%, 62% and 76% of our revenues in 2009, 2008 and 2007, respectively. Customers in the United States accounted for 24%, 13% and 16% of our revenues in 2009, 2008 and 2007, respectively. Customers in Taiwan accounted for 11%, 16% and 6% of our revenues in 2009, 2008 and 2007, respectively, while our remaining revenues were from customers in the rest of Asia and in Europe.

Project Licenses

We form product development and licensing relationships directly with semiconductor companies. In these relationships, the prospective licensee's implementation of our technologies typically includes customized development. Usually, these relationships involve both engineering work to implement our technology in the specified product and licensing the technology for manufacture and sale of the product. Although the precise terms contained in our macro development and license agreements vary, they generally include licensing fees, development fees for customizations based on the achievement of specified development milestones, and royalties. The vast majority of our contracts allow for milestone

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billings based on work performed. If we perform the contracted services, usually the licensee is obligated to pay the license fees even if the licensee cancels the project prior to completion. The agreements often also provide for the payment of additional contract fees if we provide engineering or manufacturing support services related to the manufacture of the product. Provisions in our memory license agreements generally require the payment of royalties to us based on the future sale or manufacture of products utilizing our technologies. Generally, our project licenses grant rights on a non-exclusive, non-transferable basis, limited to the use of our technology as modified for the project covered by the license agreement. Our license agreements generally have a fixed term and are subject to renewal. Each new project requires a separate agreement or an addendum to modify an existing agreement.

We have license agreements with many companies, including, but not limited to, Agilent Technologies, Analog Devices, Inc., Broadcom Corporation, Dialog Semiconductor, Entropic Communications, Inc., eSilicon Corporation, Fujitsu Ltd., Himax Technologies, Ltd., Hitachi, Ltd., Kawasaki Micoroelectronics, Inc., LG Electronics, Inc., LSI Logic Corporation, Marvell Semiconductor, Inc., Matsushita Communication Industrial Co., Ltd., Mindspeed Technologies, Inc., National Semiconductor Corporation, NEC, Nexuschips Co. Ltd., Open-Silicon, Inc., Orise Technology Co. Inc., Philips Semiconductors, Inc., Pixelworks, Inc., Pixim, Inc., Progate Group Corporation, Realtek Semiconductor Corporation, Rohm Co. Ltd, Silterra Ltd., SMIC, Sanyo Electric Co., Ltd., Sony Corporation, TSMC, UMC, Via Technologies, Inc., Xilinx, Inc., and Yamaha Corporation.

Technology Licenses

We also offer our technology to semiconductor companies and foundries through 1T-SRAM and I/O technology license agreements, under which we grant the licensee the additional right to create and modify designs to offer to its own customers or use internally. The contract fees associated with these arrangements typically require the licensee to pay us to port our technology to its manufacturing process and develop a template design that the licensee will be able to use to generate future designs. These agreements also may obligate the licensee to pay contract fees upon the achievement of specified development milestones and may provide for the payment of additional contract fees for engineering or manufacturing support services. Our memory technology license agreements include royalty provisions based on the sale or manufacture of products utilizing our technologies. The technology licenses are non-transferable and authorize the licensee to modify designs for its customers or internal use from the template design that we provide under the agreement. Typically, the template design applies only to a specified manufacturing process generation or specific application. The licensee may add future process generations or uses to the license agreement for additional contract fees.

Research and Development

Our ability to compete in the future depends on improving our technology to meet the market's increasing demand for higher performance and lower cost requirements. We have assembled a team of highly skilled engineers whose activities are focused on developing even higher density, lower power consumption, higher speed and lower cost memory and I/O IP designs. We expect to continue to focus our research and development efforts by extending our I/O IP, 1T-SRAM and 1T-Flash technologies to smaller process geometries, porting our technology to additional foundries and semiconductor manufacturing facilities. In addition, our development of the Bandwidth Engine IC will require the hiring of specialized chip design engineers as well significant fabrication and testing costs, including mask costs, for initial product development in 2010.

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As of December 31, 2009, we employed 125 individuals in engineering and research and development, of which 52 are employed in our facility in Hyderabad, India. For the years ended December 31, 2009, 2008 and 2007, research and development expenditures totaled approximately $19.3 million, $17.2 million and $12.2 million, respectively.

Sales and Marketing

As of December 31, 2009, we had 14 sales, marketing and application engineering personnel managing and supporting our licensing activities. Our sales and marketing personnel are located in the United States and Japan. In addition to our direct sales team, we sell our technologies through sales representatives in Europe and Asia. The sales personnel manage the negotiation of license agreements, provide technical support during the sales cycle to licensees and manage delivery under the contracts.

Our overall revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue. For the year ended December 31, 2009, NEC, TSMC and Fujitsu represented 44%, 10% and 10% of total revenue, respectively. For the year ended December 31, 2008, NEC and TSMC represented 55% and 13% of total revenue, respectively. For the year ended December 31, 2007, NEC represented 70% of total revenue.

Intellectual Property

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success, and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights. As of December 31, 2009, we held approximately 102 U.S. and approximately 50 foreign patents on various aspects of our technology, with expiration dates ranging from 2012 to 2027. We currently have approximately 50 pending patent applications in the U.S. and abroad. There can be no assurance that others will not independently develop similar or competing technology or design around any patents that may be issued to us, or that we will be able to enforce our patents against infringement.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights are subject to a number of factors, particularly those described in Part I, Item 1A, "Risk Factors."

Competition

The markets for our memory and I/O technologies are highly competitive. We believe that the principal competitive factors are:

•density and cost;

•power consumption;

•speed;

•portability to different manufacturing processes;

•scalability to different manufacturing process generations;

•reliability and low manufacturing costs;

•interface requirements;

•the ease with which technology can be customized for and incorporated into customers' products; and

•level of technical support provided.

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In order to remain competitive, we believe we must continue to provide higher density, lower power consumption, higher speed and lower cost technology solutions. Our 1T-SRAM technologies compete primarily with traditional SRAM, which is currently the preferred choice for embedded memory solutions in SoCs requiring less density, and embedded DRAM. Companies providing traditional SRAM embedded memories include ARM Holdings PLC and Virage Logic Corporation. Embedded DRAM is offered by major foundries and IC suppliers such as TSMC, Toshiba and International Business Machines Corporation, or IBM, among others. Foundries offering embedded DRAM are also able to provide their customers with IC design services, include memory designs for their customers ICs. In that case, the cost of the embedded memory and design are included in the wafer cost charged by the foundry. In these cases, companies would not have to license the use of their memory design from a memory provider like us, but would get the memory design from their foundry partner. We have licensed our 1T-SRAM technology to TSMC, and, under that license, TSMC is able to offer embedded DRAM solutions directly to its customers, obviating the need for those customers to obtain a license and do business directly with us. While TSMC does pay us royalties based on wafers it produces that incorporate our technology, these royalties are lower than the license and royalty fees we have historically received from customers that came to us for a technology license and memory design.

Not all embedded memory applications benefit sufficiently from the technological advantages offered by our 1T-SRAM to justify the increased cost to the licensee. Our licensees and prospective licensees can meet their current needs for embedded memory using other memory solutions with different cost and performance parameters. For example, our technologies are not suitable for replacing lower-cost traditional DRAM memory chips if higher access speed is unnecessary. In addition, alternative solutions may be more cost-effective for memory block sizes of less than one megabit, or applications in which the embedded memory portion is less than 20% of the total chip area.

Moreover, some companies assess greater uncertainty and risk in relying on the newer generations of 1T-SRAM technologies. As a result, our ability to compete effectively may be limited because such companies may prefer to use more established traditional memory solutions that are freely available without a license. In the current macroeconomic environment, we believe that, notwithstanding the competitively superior features of our technology, companies, including some of our current and past licensees, will continue to seek new ways to reduce their costs, which could include modifying designs to accommodate traditional memory solutions instead of licensing 1T-SRAM from us or our technology licensees.

Our I/O IP solutions compete with offerings from Synopsys, Inc. and other IP providers, as well as the internal design teams of customers. We believe our interface solutions can meet the need for faster rates of data transfer, such as 10Gbps and greater, which the industry is striving for. Time to market is critical for our customers. Therefore, having IP that conforms to widely-used industry protocols or standards is an important advantage of our I/O technology to reduce the amount of design time required to produce an integrated circuit.

Employees

As of December 31, 2009, we had 152 employees, consisting of 125 in research and development and engineering, 14 in sales, marketing and application engineering and 13 in finance and administration. We believe our future success depends, in part, on our ability to continue to attract and retain qualified technical and management personnel, particularly highly skilled design engineers involved in new product development, for which competition is intense. We believe that our employee relations are good.

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Available Information

We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934 as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read and copy any materials we file with the SEC, at the SEC's Public Reference Room at 450 Fifth Street, NW, Washington, DC 20549. You can obtain additional information about the operation of the Public Reference Room by calling the SEC at 1.800.SEC.0330. In addition, the SEC maintains a website (www.sec.gov) that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Executive Officers

The names of our executive officers and certain information about them are set forth below:

Leonard Perham 66 President and Chief Executive Officer James W. Sullivan 41 Vice President of Finance and Chief Financial Officer Sundari Mitra 46 Executive Vice President of Engineering David DeMaria 48 Vice President of Business Operations

Leonard Perham, Mr. Perham was appointed President and Chief Executive Officer in November 2007. Mr. Perham was one of the original investors of MoSys and served on our Board of Directors from 1991 to 1997. Until his retirement from Integrated Device Technology, Inc., or IDT, in 2000, Mr. Perham served as its Chief Executive Officer from 1991 and President and board member from 1986. In his role at IDT, one of our early investors, Mr. Perham served on our board of directors from 1991 to 1997. Mr. Perham has served as chairman of the board of directors of NetLogic Microsystems, a fabless semiconductor company, and has been a venture partner with AsiaTech Management, a venture capital firm. Prior to joining IDT, Mr. Perham was President and CEO of Optical Information Systems, Inc., a division of Exxon Enterprises. He was also a member of the founding team at Zilog Inc. and held management positions at Advanced Micro Devices and Western Digital. Mr. Perham received a Bachelor of Science degree in Electrical Engineering from Northeastern University.

James W. Sullivan, Mr. Sullivan became our Vice President of Finance and Chief Financial Officer in January 2008. From July 2006 until January 2008, Mr. Sullivan served as Vice President of Finance & Chief Financial Officer at Apptera, Inc., a venture-backed company providing software for mobile advertising, search and commerce. From July 2002 until June 2006, Mr. Sullivan was the Vice President of Finance and Chief Financial Officer at 8x8, Inc., a provider of voice over Internet protocol communication services. Mr. Sullivan's prior experience includes various positions at 8x8, Inc. and PricewaterhouseCoopers LLP. He received a Bachelor of Science degree in Accounting from New York University and is a Certified Public Accountant.

Sundari Mitra, Ms. Mitra became our Executive Vice President of Engineering in June 2009. Prior to joining the Company, Ms. Mitra founded and served as Chief Executive Officer of Prism Circuits from its inception in February 2006 until our acquisition of Prism Circuits on June 5, 2009. Prior to joining Prism Circuits, Ms. Mitra served as a Director of Engineering at Sun Microsystems, Inc. from June 2002 to August 2004. Ms. Mitra holds a Masters of Science degree in Electrical Engineering from

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the University of Illinois and a Bachelors of Science degree in Electrical Engineering from Baroda University in India.

David DeMaria, Mr. DeMaria became our Vice President of Business Operations in August 2008. From November 2007 until August 2008, Mr. DeMaria served as Senior Vice President at Apache Design Solutions, an electronic design automation software company. From January 2006 until November 2007, Mr. DeMaria was Chief Executive Officer of Optimal Corporation, an electronic design automation software company that he helped grow and ultimately merge with Apache Design Solutions. From October 1999 to March 2004, Mr. DeMaria served in various positions, including Executive Vice President of the systems business unit and Senior Vice President of worldwide marketing and strategy, at Cadence Design Systems. Mr. DeMaria attended Boston University for a Bachelor of Science degree in Computer Engineering.

Company Overview

We design, develop, market and license embedded memory intellectual property, or IP, used by the semiconductor industry and electronic product manufacturers. We have developed a patented semiconductor memory technology, called 1T-SRAM, which offers a combination of high density, low power consumption and high speed at performance and cost levels that other available memory technologies do not match. We license this technology to companies that incorporate, or embed, memory on complex integrated circuits, or ICs, such as system-on-chips, or SoCs.

We signed our first license agreement related to our 1T-SRAM technologies at the end of the fourth quarter of 1998 and recognized our first licensing revenue from our 1T-SRAM technologies in the first quarter of 2000. Since then, we have introduced improved and enhanced versions of our technology, such as 1T-SRAM-R, 1T-SRAM-M, and 1T-SRAM-Q. In 2005, we began delivering our 1T-SRAM CLASSIC Memory Macro products to licensees. These macros are pre-configured, silicon-proven and high-density solutions offering customers rapid memory block integration into their SoC designs with minimal additional customization.

We generate revenue from the licensing of our memory technology, and our customers pay us fees for licensing, non-recurring engineering services, royalties, and maintenance and support. Royalty revenues are typically earned under our license agreements when our licensees manufacture or sell products that incorporate any of our technologies. Generally, we expect our total sales cycle, or the period from our initial discussion with a prospective licensee to our receipt of royalties from the licensee's use of our technologies, to run from 18 to 24 months. Historically, the portion of our sales cycle from the initial discussion to the receipt of license fees may run from six to 12 months, depending on the complexity of the proposed project and degree of development services required.

In the third quarter of 2007, we acquired analog/mixed-signal integrated circuit designs, intellectual property, related assets and subsidiaries from Atmel Corporation, or Atmel, and LSI Design and Integration Corporation, or LDIC. In December 2008, as part of our initiative to exit unprofitable and non-core product lines, we announced our plan to cease all further work and sales activities on the acquired analog/mixed-signal products, close our subsidiaries in China and Romania, and eliminate approximately 90 employees in the first half of 2009.

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Industry Background

The personal computer, wireless communications, networking equipment and consumer electronics markets are characterized by intensifying competition, rapid innovation, increasing performance requirements and continuing cost pressures. To manufacture electronic products that achieve optimal performance and cost levels, semiconductor companies must produce integrated circuits that offer higher performance, greater functionality and lower cost.

Two important measures of performance are speed and power consumption. Higher speed integrated circuits allow electronic products to operate faster, enabling the performance of more functions. Reducing the power consumption of integrated circuits contributes to increased battery life and reduced heat and electro-magnetic field, generation in electronic products. Reduced power consumption also enables integrated circuit designers to overcome costly design hurdles, such as meeting the thermal limitations of low-cost packaging materials.

In addition to offering high-performance products, semiconductor companies must produce integrated circuits that are cost effective. High-density integrated circuits require less silicon, thus reducing their size and cost. Cost reductions also can be achieved by simplifying the integrated circuit's manufacturing process and improving the manufacturing yield.

To avoid the high cost of substantial redesign, semiconductor companies typically use technology that is scalable, which means it can be readily incorporated into multiple generations of manufacturing process technologies. Process technology generations are distinguished in terms of the dimension of the integrated circuit's smallest topographical features, as measured in microns (one millionth of a meter) or nanometers (one billionth of a meter) (nm). The semiconductor industry has continuously developed advanced process technologies that enable the reduction of silicon area on integrated circuits and consequently lower costs.

Importance of Integration

For decades, the semiconductor industry has continuously increased the value of integrated circuits by improving their density, power consumption, speed and cost. The main driver for these improvements has been the success of shrinking the size of the basic semiconductor building block, or transistor. Transistors have become small enough to make it economical to combine multiple functions, such as microprocessors, graphics, memory, analog components and digital signal processors, on a SoC. Highly integrated circuits such as SoCs often offer advantages in density, power consumption, speed and cost that cannot be matched using separate, discrete integrated circuits. SoCs are essential for most electronic products, such as cellular phones, video game consoles, portable media players, communication and networking equipment and internet appliances, to achieve increasing performance requirements at a reasonable cost.

For many large volume IC market opportunities, semiconductor companies and integrated device manufacturers, or IDMs, are developing and using a single complex SoC to replace two or three integrated circuits. Development costs for these complex SoCs continue to escalate at a rapid rate due to the use of lower process technology solutions (e.g., 65nm and below) resulting in greater demand for license semiconductor intellectual property. Semiconductor companies and IDMs prefer to purchase verified IP from either an IP vendor, such as us, or a foundry that manufactures their integrated circuits. Foundries may have their own internally developed IP or may license the IP from an IP vendor.

Importance of Embedded Memory

Historically, semiconductor companies implemented memory by using stand-alone integrated circuits. Rather than using stand-alone memory chips, many semiconductor companies today are

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embedding memory on SoCs in order to optimize performance and power consumption. At the same time, the increasing sophistication of electronic products is driving a rapid increase in the amount of memory required. The amount of embedded memory area on an SoC continues to grow due to the increasing complexity of embedded applications and the rich multimedia capabilities they support requiring more data and program code storage with corresponding system price and size constraints. These constraints dictate that more information is processed in local memories on the chip rather than in discrete external memory devices.

The high cost of incorporating the memory component represents a major challenge to achieving high levels of integration. As embedded memories account for an increasing percentage of the size of a highly integrated circuit, they are often the slowest or limiting function in the circuit. Not only must integrated circuits contain a larger amount of embedded memory, this memory must be dense enough to be economically attractive and must offer sufficiently high speed and low power consumption. In many applications, embedded memory has become a crucial design consideration for determining the overall cost and performance of highly integrated circuits and the growing number of electronic products in which they are incorporated. In addition, embedded memory density requirements are continually increasing.

The most common form of embedded memory today is implemented using traditional static random access memory, or SRAM. This technology is in the public domain and can be designed by any semiconductor company. As memory requirements increase, however, traditional SRAM becomes more expensive compared to the total cost of the integrated circuit because it requires a substantial amount of silicon area due to its low density and consumes a significant amount of power when operating at high speeds.

To overcome the density limitations of traditional SRAM, some SoC manufacturers have utilized embedded dynamic random access memory, or embedded DRAM. While embedded DRAM is denser than traditional SRAM, it is dramatically slower. Manufacturing embedded DRAM also requires additional process steps and results in lower yields, which translate into increased manufacturing time and cost. Additionally, because of its more complex interface requirements, embedded DRAM is more difficult to incorporate on integrated circuits, leading to a higher risk of failure. As integrated circuit designers have experimented with embedded DRAM, they have discovered that these limitations of embedded DRAM preclude its use in many applications. Therefore, traditional SRAM continues to be the most widely used technology for embedded memory. One of the major challenges for the semiconductor industry today is to find an embedded memory solution that combines high-density, low-power consumption, high-speed and low cost.

Our Solution

Our innovative 1T-SRAM technologies provide major advantages over traditional SRAM in density, power consumption and cost, making it more economical for designers to incorporate large amounts of embedded memory in their designs. In addition, our 1T-SRAM technologies offer all the benefits of traditional SRAM, such as high-speed, simple interface and ease of manufacturability. Our 1T-SRAM technologies can achieve these advantages while utilizing standard logic manufacturing processes and providing the simple, standard SRAM interface that designers are accustomed to.

High Density

The high density of our 1T-SRAM technologies stems from the use of a single-transistor, or 1T, which is similar to DRAM, with a storage cell for each bit of information. Embedded memory utilizing our 1T-SRAM technologies is typically two to three times denser than the six-transistor storage cells used by traditional SRAM. Increased density enables manufacturers of electronic products, such as

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cellular phones, video game consoles and digital cameras and camcorders, to incorporate additional functionality into a single integrated circuit, resulting in overall cost savings.

Low Power Consumption

Embedded memory utilizing our 1T-SRAM technologies can consume as little as one-half the active power and generates less heat than traditional SRAM when operating at the same speed. This facilitates longer battery life, reduces system level heat dissipation costs and enables reliable operation using lower cost packaging.

High Speed

Embedded memory utilizing our 1T-SRAM technologies typically provides speeds equal to or greater than the speeds of traditional SRAM, particularly for larger memory sizes. Our 1T-SRAM memory designs can sustain random access cycle times of less than three nanoseconds.

Demonstrate Manufacturing Process Independence

We have been able to implement our technology with minimal changes to the standard logic process flow. 1T-SRAM's portability, or the ease with which it can be implemented in different semiconductor manufacturing facilities, has been proven operational in the fabrication of chips at the world's largest independent foundries, including Silterra Ltd., or Silterra, Taiwan Semiconductor Manufacturing Co., Ltd., or TSMC, United Microelectronics Corporation, or UMC, Chartered Semiconductor Manufacturing Ltd., or Chartered, and Semiconductor Manufacturing International Corporation, or SMIC. It has also been proven in the manufacturing processes of integrated device manufacturers, such as Fujitsu Limited, or Fujitsu, and NEC Electronics, or NEC. 1T-SRAM's scalability, or the ease with which it can be implemented in different generations of manufacturing processes, has already been demonstrated in the fabrication of chips in 0.25 micron, 0.18 micron, 0.15 micron, 0.13 micron, 90nm, and 65nm process generations, with smaller geometries under development. We expect our technology to continue to scale to future process generations. This portability and scalability provides for wide availability, inexpensive implementation and quick product time to market for our licensees and has demonstrated our success with the large foundries.

Our Strategy

Our strategy is to increase our percentage coverage of embedded IP in targeted SoCs. We believe the high growth connected consumer, converged mobile, and embedded computing market segments provide significant growth opportunities for our embedded memory IP. We intend to achieve this goal by continuing to license our technology on a non-exclusive and worldwide basis to foundries, IDMs and semiconductor companies.

The following are integral aspects of our strategy:

Target Large and Growing Markets

We target the large and growing market for SoC applications requiring large embedded memories, which are typically in excess of one megabyte, with our 1T-SRAM technologies that offer chip designers improved performance in embedded memories thus optimizing the cost and performance of the SoC.

Although our 1T-SRAM technologies are applicable to many markets, we presently focus on rapidly growing product segments within the consumer electronics and communications sectors. These sectors increasingly require embedded memory solutions with higher density, lower power consumption, higher speeds and lower cost. We also will focus over the longer term on other markets that are projected to achieve strong, long-term growth.

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For example, a target market we have penetrated is the small-to-medium-sized liquid crystal display driver interface, or DDI, integrated circuit market. Historically, the memory required by DDI integrated circuits, has been provided by separate ICs. We believe that embedded 1T-SRAM embedded on an SoC or DDI IC can provide significant cost savings due to its higher density and reduced active power consumption.

Work Closely with Semiconductor Companies and Foundries to Deliver Optimal Technology Solutions

We work closely with semiconductor companies and foundries to gain broad and detailed insight into their and their customers' current and next-generation technology requirements. This insight helps us identify trends and focus our development efforts on optimizing our technology solution, resulting in shorter product time to market and lower costs. We plan to continue to qualify and license our technology with the leading IDMs and foundries in order to provide a wide range of manufacturing choices for our customers.

Extend our Technology Offerings

Our goal is to continue to enhance our 1T-SRAM technologies and increase our share of the embedded memory market. We will continue to develop our technology in order to offer even higher-density, lower-power consumption, higher-speed and lower-cost solutions for our licensees in smaller process geometries. In addition, we will continue to identify and develop application-specific solutions for specific markets, such as for the display driver integrated circuit market. We continue to invest heavily in research to develop more advanced memory technologies, including our embedded non-volatile memory solution, 1T-FLASH.

Licensing and Distribution Strategy

We offer our technology on a non-exclusive and worldwide basis to semiconductor companies, electronic product manufacturers, foundries, intellectual property companies and design companies through product development, technology licensing and joint marketing relationships.

We license our technology to semiconductor companies who incorporate our technology into integrated circuits that they sell to their customers. In addition, we engage in joint marketing activities with foundries, intellectual property companies and design companies to promote our technology to a wide base of customers. These distribution channels have broadened the acceptance and availability of our technology in the industry. As our technology becomes available through an increasing number of channels, we believe it will be less likely that customers will have to alter their procurement practices in order to acquire our technology. We intend to continue to significantly expand this base of strategic relationships to further proliferate our technology.

Sales to customers in Japan accounted for 62%, 76% and 60% of our revenues in 2008, 2007 and 2006, respectively. Sales to customers in Taiwan accounted for 16%, 6% and 11% of our revenues in 2008, 2007 and 2006, respectively. Sales to customers in the United States accounted for 13%, 16%, and 21% of our revenues in 2008, 2007 and 2006, respectively. The remaining sales were to customers in the rest of Asia and Europe.

Project Licenses

We form product development and licensing relationships directly with semiconductor companies. In these relationships, the prospective licensee's implementation of our 1T-SRAM technologies typically includes customized development. Usually, these relationships involve both engineering work to implement our technology in the specified product and licensing the technology for manufacture and sale of the product. Although the precise terms contained in our 1T-SRAM macro development and license agreements vary, they generally include licensing fees, development fees for customizations

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based on the achievement of specified development milestones and royalties. The vast majority of our contracts allow for milestone billings based on work performed. If we perform the contracted services, usually the licensee is obligated to pay the license fees even if the licensee cancels the project prior to completion. The agreements often also provide for the payment of additional contract fees if we provide engineering or manufacturing support services related to the manufacture of the product. Provisions in all of our license agreements require the payment of royalties to us based on the future sale or manufacture of products utilizing our 1T-SRAM technologies. Generally, our project licenses grant rights on a non-exclusive, non-transferable basis, limited to the use of our technology as modified for the project covered by the license agreement. Our license agreements generally have a fixed five-year term and are subject to renewal. Each new project requires a separate agreement or an addendum to modify an existing agreement.

We have license agreements with many companies, including, but not limited to, Agilent Technologies, Analog Devices, Inc., Broadcom Corporation, Dialog Semiconductor, eSilicon Corporation, Fujitsu, Himax Technologies, Ltd., Hitachi, Ltd., Kawasaki Micoroelectronics, Inc., Keyasic Ltd., LG Electronics, Inc., LSI Logic Corporation, Marvell Semiconductor, Inc., Matsushita Communication Industrial Co., Ltd., National Semiconductor Corporation, NEC, Nexuschips Co. Ltd., Open-Silicon, Inc., Orise Technology Co. Inc., Philips Semiconductors, Inc., Pixelworks, Inc., Pixim, Inc., Progate Group Corporation, Realtek Semiconductor Corporation, Sicon Semiconductor AB, Silterra, SMIC, Sanyo Electric Co., Ltd., Sony Corporation, TSMC, UMC, Via Technologies, Inc., and Yamaha Corporation.

Design Licenses

We offer directly to our licensees customized memory designs to meet their specific design parameters. We also offer a variety of options for optimizing the design specification in order to improve performance and cost effectiveness.

Companies also can license standard off-the-shelf memory designs from us, known as CLASSIC Macros. These readily available and verified standard memory designs can assist the licensee in getting its SoC quickly to market.

Technology Licenses

We also offer our technology to semiconductor companies and foundries through 1T-SRAM technology license agreements, under which we grant the licensee the additional right to create and modify 1T-SRAM designs to offer to its own customers. The contract fees associated with these arrangements typically require the licensee to pay us to port our technology to its manufacturing process and develop a template design that the licensee will be able to use to generate future designs. These agreements also may obligate the licensee to pay contract fees upon the achievement of specified development milestones and may provide for the payment of additional contract fees for engineering or manufacturing support services. Royalties are payable based on the future sale or manufacture of products utilizing our 1T-SRAM technologies. The licenses are non-exclusive and non-transferable and authorize the licensee to modify designs for its customers from the template design that we provide under the agreement. Typically, the template design applies only to a specified manufacturing process generation. The licensee may add future process generations to the license agreement for additional contract fees.

Research and Development

Our ability to compete in the future depends on improving our technology to meet the market's increasing demand for higher performance and lower cost requirements. We have assembled a team of highly skilled engineers whose activities are focused on developing even higher density, lower power consumption, higher speed and lower cost memory designs. We expect to continue to focus our research and development efforts by extending our 1T-SRAM and 1T-FLASH technologies to smaller process geometries, porting our technology to additional foundries and semiconductor manufacturing facilities and developing new memory technologies, such as the DDI macros.

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As of December 31, 2008, we employed 164 individuals in engineering and research and development. As a result of the plan to exit the analog/mixed-signal product lines, approximately 90 of these positions in our China and Romania subsidiaries will be eliminated in the first half of 2009. For the years ended December 31, 2008, 2007, and 2006, research and development expenditures totaled approximately $17.2 million, $12.0 million and $8.2 million, respectively. Research and development expenditures related to the analog/mixed signal product lines were $5.8 million and $2.9 million for the years ended December 31, 2008 and 2007, respectively.

Sales and Marketing

As of December 31, 2008, we had 15 sales and marketing personnel managing and supporting our licensing activities. Our sales and marketing personnel are located in the United States, Japan and Korea. In addition to our direct sales team, we sell our technologies through sales representatives in Europe and Asia. The sales personnel manage the negotiation of license agreements, provide technical support during the sales cycle to licensees and administer the contracts.

Our overall revenue has been highly concentrated, with a few customers accounting for a significant percentage of our total revenue. For the year ended December 31, 2008, NEC and TSMC represented 55% and 13% of total revenue, respectively. For the year ended December 31, 2007, NEC represented 70% of total revenue. For the year ended December 31, 2006, NEC, Fujitsu and TSMC represented 27%, 25% and 10% of total revenue, respectively.

Intellectual Property

We regard our patents, copyrights, trademarks, trade secrets and similar intellectual property as critical to our success, and rely on a combination of patent, trademark, copyright, and trade secret laws to protect our proprietary rights. As of December 31, 2008, we held approximately 95 U.S. and approximately 48 foreign patents on various aspects of our memory technology, with expiration dates ranging from 2012 to 2027. We currently have approximately 64 pending patent applications in the U.S. and abroad. There can be no assurance that others will not independently develop similar or competing technology or design around any patents that may be issued to us, or that we will be able to enforce our patents against infringement.

The semiconductor industry is characterized by frequent litigation regarding patent and other intellectual property rights. Our licensees or we might, from time to time, receive notice of claims that we have infringed patents or other intellectual property rights owned by others. Our successful protection of our patents and other intellectual property rights are subject to a number of factors, particularly those described in Part I, Item 1A. "Risk Factors."

Competition

The markets for our products are highly competitive. We believe that the principal competitive factors are:

•density and cost;

•power consumption;

•speed;

•portability to different manufacturing processes;

•scalability to different manufacturing process generations;

•reliability and low manufacturing costs;

•interface requirements;

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•the ease with which technology can be customized for and incorporated into customers' products; and

•level of technical support provided.

In order to remain competitive, we believe we must continue to provide higher density, lower power consumption, higher speed and lower cost technology solutions. Our 1T-SRAM technologies compete primarily with traditional SRAM, which is currently the preferred choice for embedded memory solutions in SoCs requiring less density, and embedded DRAM. Companies providing traditional SRAM embedded memories include ARM Holdings PLC and Virage Logic Corporation. Embedded DRAM is primarily offered by DRAM suppliers, who utilize their own manufacturing process to compete in the semiconductor foundry business. Suppliers of embedded DRAM include substantial competitors such as Toshiba Ltd. and International Business Machines Corporation, or IBM, among others.

Not all embedded memory applications benefit sufficiently from technological advantages offered by our 1T-SRAM technologies to justify the increased cost to the licensee, however. Our licensees and prospective licensees can meet their current needs for embedded memory using other memory solutions with different cost and performance parameters. For example, our technologies are not suitable for replacing lower-cost traditional DRAM memory chips if higher access speed is unnecessary. In addition, alternative solutions may be more cost-effective for memory block sizes of less than one megabit, or applications in which the embedded memory portion is less than 20% of the total chip area.

Moreover, some companies assess greater uncertainty and risk in relying on our newer generations of 1T-SRAM technologies. As a result, our ability to compete effectively may be limited because such companies may prefer to use more established traditional memory solutions that are freely available without a license. In the current macroeconomic environment and decline in the semiconductor industry, we believe that, notwithstanding the competitively superior features of our technology, companies, including some of our current and past licensees will continue to seek new ways to reduce their costs, which could include modifying designs to accommodate traditional memory solutions instead of licensing 1T-SRAM from us or our technology licensees.

Our recently developed 1T-FLASH technology requires significant analysis by customers on the qualification data of this technology to address the risk versus other established technologies. However, we believe our 1T-FLASH technology achieves higher density and can be used in widely accepted semiconductor manufacturing processes. Our 1T-FLASH technology competes with technology of other IP vendors and internally developed technologies of IDMs.

Employees

As of December 31, 2008, we had 191 employees, consisting of 164 in research and development and engineering, 15 in sales and marketing and 12 in finance and administration. Under our plan to exit the analog/mixed-signal product lines, we expect to eliminate 90 research and development and engineering positions in the first half of 2009. We believe our future success depends, in part, on our ability to continue to attract and retain qualified technical and management personnel, particularly highly skilled design engineers involved in new product development, for which competition is intense. We believe that our employee relations are good.

Available Information

We were founded in 1991 and reincorporated in Delaware in September 2000. Our website address is www.mosys.com. The information in our website is not incorporated by reference into this report. Through a link on the Investor section of our website, we make available our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and any amendments to

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those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Securities Exchange Act of 1934 as soon as reasonably practicable after they are filed with, or furnished to, the Securities and Exchange Commission, or SEC. You can also read and copy any materials we file with the SEC, at the SEC's Public Reference Room at 450 Fifth Street, NW, Washington, DC 20549. You can obtain additional information about the operation of the Public Reference Room by calling the SEC at 1.800.SEC.0330. In addition, the SEC maintains a website (www.sec.gov) that contains reports, proxy and information statements, and other information regarding issuers that file electronically with the SEC, including us.

Executive Officers

The names of our executive officers and certain information about them are set forth below:

Leonard Perham 65 President and Chief Executive Officer James W. Sullivan 40 Vice President of Finance and Chief Financial Officer David DeMaria 47 Vice President of Business Operations

Leonard Perham, Mr. Perham was appointed President and Chief Executive Officer in November 2007. Mr. Perham was one of the original investors of MoSys and served on our Board of Directors from 1991 to 1997. Until his retirement from Integrated Device Technology, Inc., or IDT, in 2000, Mr. Perham served as its Chief Executive Officer from 1991 and President and board member from 1986. In his role at IDT, one of our early investors, Mr. Perham served on our board of directors from 1991 to 1997. Mr. Perham has served as chairman of the board of directors of NetLogic Microsystems, a fabless semiconductor company, and has been a venture partner with AsiaTech Management, a venture capital firm. Prior to joining IDT, Mr. Perham was President and CEO of Optical Information Systems, Inc., a division of Exxon Enterprises. He was also a member of the founding team at Zilog Inc. and held management positions at Advanced Micro Devices and Western Digital. Mr. Perham received a Bachelor of Science degree in Electrical Engineering from Northeastern University.

James W. Sullivan, Mr. Sullivan became our Vice President of Finance and Chief Financial Officer on January 18, 2008. From July 2006 until January 2008, Mr. Sullivan served as Vice President of Finance & Chief Financial Officer at Apptera, Inc., a venture-backed company providing software for mobile advertising, search and commerce. From July 2002 until June 2006, Mr. Sullivan was the Vice President of Finance and Chief Financial Officer at 8x8, Inc., a provider of voice over Internet protocol communication services. Mr. Sullivan's prior experience includes various positions at 8x8, Inc. and PricewaterhouseCoopers LLP. He received a Bachelor of Science degree in Accounting from New York University and is a Certified Public Accountant.

David DeMaria, Mr. DeMaria became our Vice President of Business Operations on August 18, 2008. From November 2007 until August 2008, Mr. DeMaria served as Senior Vice President at Apache Design Solutions, an electronic design automation software company. From January 2006 until November 2007, Mr. DeMaria was Chief Executive Officer of Optimal Corporation, an electronic design automation software company that he helped grow and ultimately merge with Apache Design Solutions. From October 1999 to March 2004, Mr. DeMaria served in various positions, including Executive Vice President of the systems business unit and Senior Vice President of worldwide marketing and strategy, at Cadence Design Systems. Mr. DeMaria attended Boston University for a Bachelor of Science degree in computer engineering.

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